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參數(shù)資料
| 型號： | M38039FFHWG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.65 MM PITCH, PLASTIC, FLGA-64 |
| 文件頁數(shù)： | 68/117頁 |
| 文件大?。?/td> | 1873K |
| 代理商： | M38039FFHWG |
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Rev.3.11
Apr 5, 2006
Page 54 of 113
REJ03B0017-0311
3803 Group (Spec.H)
<Notes concerning serial I/O3>
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
Note
Clear the serial I/O3 enable bit and the transmit enable bit to
“0” (serial I/O and transmit disabled).
Reason
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O3 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD3, RXD3, SCLK3, and
SRDY3 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O3 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD3 pin and an
operation failure occurs.
1.2 Stop of receive operation
Note
Clear the receive enable bit to “0” (receive disabled), or clear
the serial I/O3 enable bit to “0” (serial I/O disabled).
1.3 Stop of transmit/receive operation
Note
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when dat a is transmit ted and received i n the clock
synchronous serial I/O mode, any one of data transmission and
reception cannot be stopped.)
Reason
In the clock synchronous serial I/O mode, the same clock is
used for transmission and reception. If any one of transmission
and reception is disabled, a bit error occurs because
transmission and reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also
operates for data reception. Accordingly, the transmission
circuit does not stop by clearing only the transmit enable bit to
“0” (transmit disabled). Also, the transmission circuit is not
initialized by clearing the serial I/O3 enable bit to “0” (serial
I/O disabled) (refer to 1.1).
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
Note
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial
I/O3 enable bit to “0”.
Reason
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O3 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD3, RXD3, SCLK3, and
SRDY3 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O3 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD3 pin and an
operation failure occurs.
2.2 Stop of receive operation
Note
Clear the receive enable bit to “0” (receive disabled).
2.3 Stop of transmit/receive operation
Note 1 (only transmission operation is stopped)
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial
I/O3 enable bit to “0”.
Reason
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O3 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD3, RXD3, SCLK3, and
SRDY3 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O3 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD3 pin and an
operation failure occurs.
Note 2 (only receive operation is stopped)
Clear the receive enable bit to “0” (receive disabled).
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