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| 型號(hào)： | M38037M6-133FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SENSOR SST 12MM ZERO SPEED |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 71/135頁(yè) |
| 文件大?。?/td> | 2055K |
| 代理商： | M38037M6-133FP |
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71
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[I
2
C Data Shift Register (S0)] 0011
16
The I
2
C data shift register (S0: address 0011
16
) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL, and each
time one-bit data is output, the data of this register are shifted by
one bit to the left. When data is received, it is input to this register
from bit 0 in synchronization with the SCL, and each time one-bit
data is input, the data of this register are shifted by one bit to the
left. The minimum 2 cycles of system clock
φ
are required from the
rising of the SCL until input to this register.
The I
2
C data shift register is in a write enable status only when the
I
2
C-BUS interface enable bit (ES0 bit) of the I
2
C control register
(S1D: address 0014
16
) is
“
1
”
. The bit counter is reset by a write in-
struction to the I
2
C data shift register. When both the ES0 bit and
the MST bit of the I
2
C status register (S1: address 0013
16
) are
“
1,
”
the SCL is output by a write instruction to the I
2
C data shift regis-
ter. Reading data from the I
2
C data shift register is always enabled
regardless of the ES0 bit value.
[I
2
C Slave Address Registers 0 to 2 (S0D0 to S0D2)]
0FF7
16
to 0FF9
16
The I
2
C slave address registers 0 to 2 (S0D0 to S0D2: addresses
0FF7
16
to 0FF9
16
) consists of a 7-bit slave address and a read/
write bit. In the addressing mode, the slave address written in this
register is compared with the address data to be received immedi-
ately after the START condition is detected.
Bit 0: Read/write bit (RWB)
This is not used in the 7-bit addressing mode. In the 10-bit ad-
dressing mode, set RWB to
“
0
”
because the first address data to
be received is compared with the contents (SAD6 to SAD0 +
RWB) of the I
2
C slave address registers 0 to 2.
When 2-byte address data match slave address, a 7-bit slave ad-
dress which is received after restart condition has detected and
R/W data can be matched by setting
“
1
”
to RWB with software.
The RWB is cleared to
“
0
”
automatically when the stop condition is
detected.
Bits 1 to 7: Slave address (SAD0
–
SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode or the 10-bit addressing mode, the address data
transmitted from the master is compared with these bits
’
contents.
Fig. 65 Structure of I
2
C slave address registers 0 to 2
S
A
D
6 S
A
D
5 SAD4 SAD3 SAD2 SAD1SAD0 RWB
S
l
a
v
e
a
d
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s
s
I
2
C
(
S
I
2
C
(
S
I
2
C
(
S
s
D
s
0
D
0
D
l
0
l
a
1
l
a
2
a
v
:
v
:
v
:
e
a
e
a
e
a
d
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s
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s
s
s
s
s
0
s
0
s
0
F
F
F
r
e
F
r
e
F
r
e
F
g
7
1
g
8
1
g
9
1
i
s
6
)
i
s
6
)
i
s
6
)
t
e
e
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r
0
0
t
r
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