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參數(shù)資料
| 型號： | M38034M4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 116/136頁 |
| 文件大?。?/td> | 2007K |
| 代理商： | M38034M4-XXXFP |
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80
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[I2C Special Mode Control Register (S3D)]
001716
The I2C special mode control register (S3D: address 001716) con-
trols special functions such as occurrence timing of reception
interrupt request and extending slave address comparison to 3
bytes.
Bit 1: ACK interrupt control bit (ACKICON)
This bit controls the timing of I2C interrupt request occurrence at
completion of data receiving due to master reception or slave re-
ception.
When this bit is “0”, the SCL pin low hold bit (PIN) is set to “0” in
synchronization with the falling of the last SCL clock, including the
ACK clock. The SCL pin is simultaneously held low, and the I2C
interrupt request occurs.
When this bit is “1” and the ACK clock bit (ACK) is “1”, the SCL pin
low hold 2 flag (PIN2) is set to “0” in synchronization with the fall-
ing of the data’s last SCL clock, just before the ACK clock. The
SCL pin is simultaneously held low, and the I2C interrupt request
occurs again. The ACK bit can be changed after the contents of
data are confirmed by using this function.
Bit 2: I2C slave address control bit (MSLAD)
This bit controls a slave address. When this bit is “0”, only the I2C
slave address register 0 (address 0FF716) becomes valid as a
slave address and a read/write bit.
When this bit is “1”, all of the I2C slave address registers 0 to 2
(addresses 0FF716 to 0FF916) become valid as a slave address
and a read/write bit. In this case, when an address data agrees
with any one of the I2C slave address registers 0 to 2, the slave
address comparison flag (AAS) is set to “1” and the I2C slave ad-
dress comparison flag corresponding to the agreed I2C slave
address registers 0 to 2 is also set to “1”.
Bit 5: SCL pin low hold 2 flag set bit (PIN2IN)
Writing “1” to this bit initializes the SCL pin low hold 2 flag (PIN2)
to “1”.
When writing “0”, nothing is generated.
Bit 6: SCL pin low hold set bit (PIN2HD)
When the SCL pin low hold bit (PIN) becomes “0”, the SCL pin is
held low. However, the SCL pin low hold bit (PIN) cannot be set to
“0” by software. The SCL pin low hold set bit (PIN2HD) is used to ,
hold the SCL pin in the low state by software. When writing “1” to
this bit, the SCL pin low hold 2 flag (PIN2) becomes “0”, and the
SCL pin is held low. When writing “0”, nothing occurs.
Bit 7: STOP condition flag clear bit (SPFCL)
Writing “1” to this bit initializes the STOP condition flag (SPCF) to
“0”.
When writing “0”, nothing is generated.
Fig. 76 Structure of I2C special mode control register
b7b0
I2C special mode control register
(S3D : address 001716)
STOP condition flag clear bit (Note 2)
Writing “1” to this bit initializes the STOP
condition flag to “0”.
ACKI
CON
MSLAD
PIN2IN
SPFCL
ACK interrupt control bit
0 :At communication completion
1 :At falling of ACK clock and communication
completion
Slave address control bit
0 :One-byte slave address compare mode
1 :Three-byte slave address compare mode
Not used
(return “0” when read)
Not used
(Fix this bit to “0”.)
SCL pin low hold 2 flag set bit (Notes 1, 2)
Writing “1” to this bit initializes the SCL pin low
hold 2 flag to “1”.
PIN2-
HD
SCL pin low hold set bit (Notes 1, 2)
When writing “1” to this bit, the SCL pin low
hold 2 flag becomes “0” and the SCL pin is held
low.
Notes 1: Do not write “1” to these bits simultaneously.
2: return “0” when read
Not used
(Fix this bit to “0”.)
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