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參數資料
| 型號： | M38031FA-XXXKP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數： | 74/119頁 |
| 文件大?。?/td> | 1575K |
| 代理商： | M38031FA-XXXKP |
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Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 74 of 117
3803 Group (Spec.L)
Software Commands
Table 12 lists the software commands.
After setting the CPU rewrite mode select bit to “1”, execute a
software command to specify an erase or program operation.
Each software command is explained below.
Read Array Command (FF
16
)
The read array mode is entered by writing the command code
“FF
16
” in the first bus cycle. When an address to be read is input
in one of the bus cycles that follow, the contents of the specified
address are read out at the data bus (D
0
to D
7
).
The read array mode is retained until another command is
written.
Read Status Register Command (70
16
)
When the command code “70
16
” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D
0
to D
7
) by a read in the second bus cycle.
The status register is explained in the next section.
Clear Status Register Command (50
16
)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that
operation has ended in an error. To use this command, write the
command code “50
16
” in the first bus cycle.
Program Command (40
16
)
Program operation starts when the command code “40
16
” is
written in the first bus cycle. Then, if the address and data to
program are written in the 2nd bus cycle, program operation
(data programming and verification) will start.
Whether the write operation is completed can be confirmed by
read status register or the RY/BY status flag. When the program
starts, the read status register mode is entered automatically and
the contents of the status register is read at the data bus (D
0
to
D
7
). The status register bit 7 (SR7) is set to “0” at the same time
the write operation starts and is returned to “1” upon completion
of the write operation. In this case, the read status register mode
remains active until the read array command (FF
16
) is written.
The RY/BY status flag of the flash memory control register is
“0” during write operation and “1” when the write operation is
completed as is the status register bit 7.
At program end, program results can be checked by reading the
status register.
Fig 72. Program flowchart
NOTES:
1. SRD = Status Register Data
2. WA = Write Address, WD = Write Data
3. BA = Block Address to be erased (Input the maximum address of each block.)
4. X denotes a given address in the User ROM area.
Start
Write “40
16
”
SR7 =
“
1
”
or
RY/BY =
“
1
”
Read status register
Program completed
NO
YES
Write
Write address
Write data
SR4 = “0”
Program error
NO
YES
Table 12 List of software commands (CPU rewrite mode)
Command
cycle
number
First bus cycle
Second bus cycle
Mode
Address
Data
(D
0
to D
7
)
FF
16
70
16
50
16
40
16
20
16
Mode
Address
Data
(D
0
to D
7
)
Read array
Read status register
Clear status register
Program
Block erase
1
2
1
2
2
Write
Write
Write
Write
Write
X
(4)
X
X
X
X
Read
X
SRD
(1)
Write
Write
WA
(2)
BA
(3)
WD
(2)
D0
16
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PDF描述 |
|---|---|
| M38031FA-XXXSP | 256 Kbit (32K x 8) nvSRAM; Organization: 32Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOIC |
| M38031FA-XXXWG | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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參數描述 |
|---|---|
| M38037M5H-175HP#U0 | 制造商:Renesas Electronics Corporation 功能描述:8BIT CISC - Trays |
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