
2.3 Serial I/O
2-44
APPLICATION
3802 GROUP USER’S MANUAL
The communication is performed according to the timing shown below. In the slave unit, when a
synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is
processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.3.33 shows a setting of related registers.
Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers]
D
0
Byte cycle
Block transfer period
Block transfer cycle
D
1
D
2
D
7
D
0
Interval between blocks
Processing for heading adjustment
Heading adjustive time
Fig. 2.3.33 Setting of related registers [Cyclic transmission or reception of block data between
microcomputers]
Master unit
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O1 enabled
SIO1CON
Serial I/O1 control register (Address : 1A
16
)
b7
b0
Synchronous
clock : BRG/4
Not use the
S
RDY1
output
Transmit interrupt source :
Transmit shift operating completion
0
1
1
1
1
0
0
1
BRG count source : f(X
IN
)
Not be effected by
external clock
Synchronous clock : External clock
Not use the
S
RDY1
output
Transmit enabled
Receive enabled
SIO1CON
Serial I/O1 control register (Address : 1A
16
)
b7
b0
Not use the serial I/O1 transmit interrupt
Clock synchronous serial I/O
1
1
1
1
Slave unit
1
Serial I/O1 enabled
0
UARTCON
UART control register (Address : 1B
16
)
b7
P4
5
/T
X
D pin : CMOS output
0
Both of units
b0
7
BRG
b7
b0
Baud rate generator (Address : 1C
16
)
Set “division ratio – 1”