![](http://datasheet.mmic.net.cn/280000/M38023M1D512SP_datasheet_16084972/M38023M1D512SP_96.png)
2-39
3802 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Figure 2.3.25 shows a setting of serial I/O1 related registers, and Figure 2.3.26 shows a setting of
serial I/O1 transmission data.
Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data]
Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data]
Serial I/O1 synchronous clock selection bit : BRG/4
S
RDY1
output enable bit : Not use the
S
RDY1
signal output function
Transmit interrupt source selection bit : Transmit shift operating
completion
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
0
Serial I/O1 transmit interrupt enable bit : Interrupt disabled
ICON1
Interrupt control register 1 (Address : 3E
16
)
b7
Serial I/O1 transmit interrupt request bit
Using this bit, check the completion of
transmitting 1-byte base data.
“1” : Transmit shift completion
IREQ1
Interrupt request register 1 (Address : 3C
16
)
b7
0 0
1
SIO1CON
Serial I/O1 control register (Address : 1A
16
)
b7
0
0
1
1
BRG count source selection bit : f(X
IN
)
1
b0
0
b0
b0
0
P4
5
/T
X
D P-channel output disable bit : CMOS output
UARTCON
UART control register (Address : 1B
16
)
b7
b0
7
Set “division ratio – 1”
BRG
Baud rate generator (Address : 1C
16
)
b7
b0
Set a transmission data.
Check that transmission of the previous data is
completed before writing data (bit 3 of the
Interrupt request register 1 is set to “1”).
TB/RB
Transmit/Receive buffer register (Address : 18
16
)
b7
b0