
2-27
3802 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Fig. 2.3.9 Structure of Interrupt edge selection register
Fig. 2.3.8 Structure of Serial I/O2 register
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Function
Serial I/O2 register (SIO2) [Address : 1F
16
]
A shift register for serial transmission and reception.
At transmitting : Set a transmission data.
At receiving : Store a reception data.
G
B
0
1
2
3
4
5
6
7
At reset
R W
G
W
R
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
1
2
3
0
0
0
0
Interrupt edge selection register (INTEDGE) [Address : 3A
16
]
Name
4
5
6
7
0
0
0
0
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
INT
0
interrupt edge
selection bit
INT
1
interrupt edge
selection bit
Nothing is allocated for this bit. This is a write
disabled bit.When this bit is read out, the value is “0.”
INT
2
interrupt edge
selection bit
INT
3
interrupt edge
selection bit
INT
4
interrupt edge
selection bit
Nothing is allocated for these bits. These are write disabled
bits. When these bits are read out, the values are “0.”