
APPLICATION
2.6 Processor mode
2-64
3802 GROUP USER’S MANUAL
2.6 Processor mode
2.6.1 Memory map of processor mode
Fig. 2.6.1 Memory map of processor mode related register
2.6.2 Related register
Fig. 2.6.2 Structure of CPU mode register
003B
16
CPU mode register (CPUM)
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
CPU mode register (CPUM) [Adress : 3B
16
]
B
Name
Processor mode bits
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
Function
At reset
R W
0
0
1
2
3
4
5
6
7
6
0
0
0
0
0
0
00 : Single-chip mode
01 : Memory expansion mode
10 : Microprocessor mode
11 : Not available
0 : 0 page
1 : 1 page
Stack page selection bit
6
An initial value of bit 1 is determined by a level of the CNV
SS
pin.