
3-13
3800 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode (1)
Fig. 3.1.3 Timing diagram (in memory expansion mode and microprocessor mode) (1)
Timing Diagram in Microprocessor Mode
t
WL(
φ
)
t
WH(
φ
)
t
C(
φ
)
φ
t
d(
φ
-AH)
t
d(
φ
-AL)
t
d(
φ
-SYNC)
t
v(
φ
-AH)
t
v(
φ
-AL)
t
v(
φ
-SYNC)
t
d(
φ
-WR)
t
v(
φ
-WR)
t
SU(ONW-
φ
)
t
h(
φ
-ONW)
t
SU(DB-
φ
)
t
h(
φ
-DB)
t
d(
φ
-DB)
t
v(
φ
-DB)
t
d(RESET- RESET
OUT
)
AD
15
–AD
8
AD
7
–AD
0
SYNC
RD,WR
ONW
DB
0
–DB
7
(At CPU reading)
DB
0
–DB
7
(At CPU writing)
RESET
φ
RESET
OUT
t
v(
φ
- RESET
OUT
)
0.5 V
CC
0.8 V
CC
0.2 V
CC
0.5 V
CC
0.5 V
CC
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
0.5 V
CC
0.5 V
CC
0.5 V
CC
0.5 V
CC
0.5 V
CC