
80
M37906M4C-XXXFP, M37906M4C-XXXSP, M37906M4H-XXXFP
M37906M4H-XXXSP, M37906M6C-XXXFP, M37906M6C-XXXSP
M37906M8C-XXXFP, M37906M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e param
etric
lim
its are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
WIT mode
When the WIT instruction is executed with the system clock stop se-
lect bit at WIT (bit 3 of the particular function select register 1 in Fig-
ure 87) being “0”,
φBIU, φCPU, and divide clocks Wf32 and Wf512 are
inactive with the “L“ state. However, the oscillation circuit, PLL circuit,
input clock fXIN, system clock fsys,
φ1, and peripheral devices’ clocks
f1 to f4096 remain active. Therefore, BIU and CPU are inactive,
whereas timers A and B, serial I/O, and the A-D converter, which use
the peripheral devices’ clocks f1 to f4096, are still active. Note that the
watchdog timer is inactive.
On the other hand, when the WIT instruction is executed with the
system clock stop select bit at WIT being “1”, the oscillation circuit,
PLL circuit, and input clock fXIN are active, while system clock fsys,
φBIU, φCPU, and peripheral devices’ clocks are inactive. As a result,
the A-D converter and watchdog timer, which use peripheral devices’
clocks f1 to f4096, Wf32 and Wf512, become inactive. At this time, tim-
ers A and B are active only in the event counter mode, and serial
I/O communication is active only while an external clock is selected.
If the internal peripheral devices are not used in the WIT mode, the
latter is better because the current dissipation is more saved. Note
that the system clock stop select bit at WIT needs to be set to “1” im-
mediately before execution of the WIT instruction and cleared to “0”
immediately after the WIT mode is terminated.
The WIT state is terminated by acceptance of an interrupt request,
and then, supply of
φBIU and φCPU will restart. Since the oscillation
circuit, PLL circuit, and clock input fXIN are active in the WIT mode,
an interrupt processing can be executed just after the WIT mode ter-
mination.