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參數(shù)資料
| 型號： | M37905F8CSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 16位CMOS微機 |
| 文件頁數(shù)： | 20/34頁 |
| 文件大小： | 362K |
| 代理商： | M37905F8CSP |
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M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
20
Table 2. Software commands (CPU reprogramming mode)
Command
Read Array
Read Status Register
Clear Status Register
Programming
Block Erase
Erase All Block
Address
X
(Note 2)
X
X
X
X
X
FF
16
70
16
50
16
40
16
20
16
20
16
1st cycle
2nd cycle
Notes 1:
At software commands
’
input, the high-order byte of data (D
8
–
D
15
) is ignored.
2:
X = An arbitrary address in the user ROM area. (Note that A
0
=
“
0
”
.)
3:
SRD = Status Register Data
4:
WA = Write Address, WD = Write Data (16 bits).
5:
Block address: the maximum address of each block must be input. Note that address A
0
=
“
0
”
.
Mode
Write
Write
Write
Write
Write
Write
(D
0
to D
7
)
Data
Address
—
X
—
WA
(Note 4)
BA
(Note 5)
X
—
SRD
(Note 3)
—
WD
(Note 4)
D0
16
20
16
Mode
—
Read
—
Write
Write
Write
Block Erase Command (20
16
/D0
16
)
Writing command code
“
20
16
”
at the 1st bus cycle and writing confir-
mation command code
“
D0
16
”
and the maximum address of the
block (Note that address A
0
=
“
0
”
.) at the subsequent 2nd bus cycle
initiate the automatic erase (erasing and erase verification) operation
for the specified block.
The completion of the automatic erase operation is confirmed by a
read of the flash memory control register. The RY/BY status bit of the
flash memory control register goes
“
0
”
simultaneously with start of
the automatic erase operation; and also, it goes
“
1
”
simultaneously
with completion of it.
Before execution of the next command, be sure to confirm that the
RY/BY status bit is set to
“
1
”
(READY). During the automatic erase
operation, writing of commands and access to the flash memory
must not be performed.
Simultaneously with start of the automatic erase, the read status reg-
ister mode is automatically active. In this case, the read status regis-
ter mode is retained until the next read array command (FF
16
) is
written or until the reset is performed by using the flash memory re-
set bit.
Reading out the status register after the automatic erase operation
is completed reports the result of it. For details, refer to the section
on the status register.
Figure 10 shows an example of the block erase flowchart.
Data
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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