![](http://datasheet.mmic.net.cn/30000/M37902FHCGP_datasheet_2360019/M37902FHCGP_51.png)
7902 Group User's Manual
2–24
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
Fig. 2.5.2 Pin configuration in each processor mode (top view)
n
Single-chip mode
49
35
34
36
39
NMI
P30/RDY
P4
2
/HLDA
D
1
/LA
1
n
Memory expansion and Miocroprocessor modes
40
37
36
38
35
34
33
32
31
39
64
63
62
61
30
29
28
27
26
25
24
23
22
21
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
79
78
77
76
75
74
73
72
71
69
68
67
66
65
70
80
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P4
1
/f
1
P81/CTS0/CLK0
P82/RXD0
P83/TXD0
VSS
AVSS
VREF
VCC
AVCC
V
SS
P73/AN3
P84/CTS1/RTS1/INT4
P85/CTS1/CLK1
P86/RXD1
MD1
VCC
VSS
XOUT
XIN
P4
0
P4
2
VCONT
RESET
MD0
P10
3
P10
4
P10
5
P10
6
P10
7
P10
1
P10
2
P11
0
P11
1
P11
2
P11
3
P11
4
P11
5
P11
6
P11
7
P0
0
P0
1
P0
2
P0
3
P0
4
P0
5
P0
7
P0
6
P1
0
P1
1
P1
2
P15
P25
P24
P23
P20
P17
P22
P21
P16
P3
3
P3
1
P3
2
P4
5
P6
0
/TA4
OUT
P6
1
/TA4
IN
P6
2
/INT
0
P6
3
/INT
1
P6
4
/INT
2
P6
5
/TB0
IN
P6
6
/TB1
IN
P5
0
/TA0
OUT
/RTP0
0
P5
1
/TA0
IN
/RTP0
1
P5
2
/TA1
OUT
/RTP0
2
P5
3
/TA1
IN
/RTP0
3
P5
4
/TA2
OUT
/RTP1
0
/KI
0
P5
5
/TA2
IN
/RTP1
1
/KI
1
P5
6
/TA3
OUT
/RTP1
2
/KI
2
P5
7
/TA3
IN
/RTP1
3
/KI
3
P4
6
P4
4
P4
3
P27
P26
P4
7
P6
7
/TB2
IN
P7
0
/AN
0
P74/AN4/(INT3)
P75/AN5/(INT4)
P76/AN6/DA0
P77/AN7/ADTRG/DA1/(INT2)
P80/CTS0/RTS0/DA2/INT3
NMI
P87/TXD1
P100
P7
1
/AN
1
P7
2
/AN
2
P30
BYTE
P1
3
P1
4
Outline: 100P6S-A
40
37
38
32
33
31
64
63
62
61
3
2
1
4
5
6
7
8
9
10
11
12
13
14
60
59
58
57
56
55
54
53
52
51
50
48
47
46
45
44
43
42
41
100
79
78
77
76
75
74
73
72
71
69
68
67
66
65
70
80
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P4
1
/f
1
P81/CTS0/CLK0
P82/RXD0
P83/TXD0
V
SS
P73/AN3
P84/CTS1/RTS1/INT4
P85/CTS1/CLK1
P86/RXD1
MD1
VCC
VSS
XOUT
XIN
VCONT
RESET
MD0
A
3
A
4
A
5
A
6
A
7
A
1
A
2
P11
0
/A
8
P11
1
/A
9
P11
2
/A
10
P11
3
/A
11
P11
4
/A
12
P11
5
/A
13
P11
6
/A
14
P11
7
/A
15
P0
0
/A
16
P0
1
/A
17
P0
2
/A
18
P0
3
/A
19
P0
4
/A
20
P0
5
/A
21
P0
7
/A
23
P0
6
/A
22
D
0
/LA
0
D
2
/LA
2
D5/LA5
P25/D13
P24/D12
P23/D11
P20/D8
D7/LA7
P22/D10
P21/D9
D6/LA6
RD
BLW
P4
5
/CS
1
P6
0
/TA4
OUT
P6
1
/TA4
IN
P6
2
/INT
0
P6
3
/INT
1
P6
4
/INT
2
P6
5
/TB0
IN
P6
6
/TB1
IN
P5
0
/TA0
OUT
/RTP0
0
P5
1
/TA0
IN
/RTP0
1
P5
2
/TA1
OUT
/RTP0
2
P5
3
/TA1
IN
/RTP0
3
P5
4
/TA2
OUT
/RTP1
0
/KI
0
P5
5
/TA2
IN
/RTP1
1
/KI
1
P5
6
/TA3
OUT
/RTP1
2
/KI
2
P5
7
/TA3
IN
/RTP1
3
/KI
3
P4
6
/CS
2
P4
4
/CS
0
P4
3
/HOLD
P27/D15
P26/D14
P4
7
/CS
3
P6
7
/TB2
IN
P7
0
/AN
0
P74/AN4/(INT3)
P75/AN5/(INT4)
P76/AN6/DA0
P77/AN7/ADTRG/DA1/(INT2)
P80/CTS0/RTS0/DA2/INT3
VSS
AVSS
VREF
VCC
AVCC
P87/TXD1
A0
P7
1
/AN
1
P7
2
/AN
2
BYTE
D
3
/LA
3
D
4
/LA
4
30
29
28
27
26
25
24
23
22
21
15
16
17
18
19
20
Each function of these pins in the single-chip mode
is different from that in the memory expansion or
microprocessor mode.
Each function of these pins in the single-chip mode
is different from that in the memory expansion or
microprocessor mode.
P4
0
/ALE
P3
3
/BHW