![](http://datasheet.mmic.net.cn/30000/M37902FHCGP_datasheet_2360019/M37902FHCGP_450.png)
7902 Group User’s Manual
21-33
APPENDIX
Appendix 2. Control registers
0
1
2
3
6 to 4
7
0
1
2
3
4
5
6
7
CS0 control register L (Address 8016)
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: This bit is “0” when Vss-level voltage is applied to pin BYTE; this bit is “1” when Vcc-level voltage is applied.
2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) is “1.”
3: When Vcc-level voltage is applied to pin BYTE, “normal access” is selected regardless of this bit’s value.
4: This bit’s contents are invalid in the single-chip mode. (CS0 output disabled)
5: This bit is “0” when Vss-level voltage is applied to pin MD0; this bit is “1” when Vcc-level voltage is applied. (Fixed to “1.”)
The input level at pin BYTE is read out.
0 : 16-bit width
1 : 8-bit width
0 : RDY control is valid.
1 : RDY control is invalid.
0 : Normal access
1 : Burst ROM access
0 : No recovery cycle is inserted at access to area CS0.
1 : Recovery cycle is inserted at access to area CS0.
0 : CS0 output is disabled. (P44 functions as a
programmable I/O port pin.)
1 : CS0 output is enabled. (P44 functions as pin CS0.)
Bit name
Bit
Function
At reset
R/W
Area CS0 bus cycle select bit 0
External data bus width select bit
RDY control bit
(Note 2)
The value is “0” at reading.
Burst ROM access select bit
(Note 3)
Recovery cycle insert select bit
CS0 output select bit
(Note 4)
RW
RO
RW
—
RW
0
1
(Note 1)
0
1
(Note 5)
0 0 : 1
φ + 1φ
0 1 : 1
φ + 2φ
1 0 : 1
φ + 3φ
1 1 : 2
φ + 2φ
b0
b1
0 0 : 2
φ + 3φ
0 1 : 2
φ + 4φ
1 0 : 3
φ + 3φ
1 1 : 3
φ + 4φ
b0
b1
(Area CS0 bus cycle select
bit 1 = 0)
(Area CS0 bus cycle select
bit 1 = 1)
0: Mode 0 (A block can be set to 16-Mbyte space.)
1: Mode 1 (Area CS0 start address is set in bank 0.)
CS0 control register H (Address 8116)
Bit name
Bit
Function
At reset
R/W
Area CS0 block size select bits
Area CS0 bus cycle select bit 1
The value is “0” at reading.
Area CS0 setting mode select bit
0 0 0 : 0 byte (Area CS0 is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
1
0
1
RW
—
RW
The combination of this bit and the area CS0 bus cycle
select bit 0 selects the bus cycle.
0 : 1
φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2
φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
Reference
3-12
3-5
3-12
Reference
3-13