參數(shù)資料
型號(hào): M378T6553BG0-CC
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR2 Unbuffered SDRAM MODULE
中文描述: 無(wú)緩沖DDR2的內(nèi)存模塊
文件頁(yè)數(shù): 17/23頁(yè)
文件大?。?/td> 367K
代理商: M378T6553BG0-CC
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
(0
°
C < T
CASE
< 95
°
C; V
DDQ
= 1.8V + 0.1V; V
DD
= 1.8V + 0.1V)
Refresh Parameters by Device Density
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
75
105
127.5
195
tbd
ns
Average periodic refresh interval
tREFI
0
°
C
T
CASE
85
°
C
7.8
7.8
7.8
7.8
7.8
μ
s
85
°
C
<
T
CASE
95
°
C
3.9
3.9
3.9
3.9
3.9
μ
s
Speed
DDR2-533(D5)
DDR2-400(CC)
Units
Bin (CL - tRCD - tRP)
4 - 4 - 4
3 - 3 - 3
Parameter
min
max
min
max
tCK, CL=3
5
8
5
8
ns
tCK, CL=4
3.75
8
5
8
ns
tCK, CL=5
-
-
-
-
ns
tRCD
15
15
ns
tRP
15
15
ns
tRC
55
55
ns
tRAS
40
70000
40
70000
ns
Parameter
Symbol
DDR2-533
DDR2-400
Units
Notes
min
max
min
max
DQ output access time from
CK/CK
tAC
-500
+500
-600
+600
ps
DQS output access time
from CK/CK
tDQSCK
-450
+450
-500
+500
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min(tCL,
tCH)
x
min(tCL,
tCH)
x
ps
20,21
Clock cycle time, CL=x
tCK
3750
8000
5000
8000
ps
24
DQ and DM input hold time
tDH
225
x
275
x
ps
15,16,
17
DQ and DM input setup
time
tDS
100
x
150
x
ps
15,16,
17
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