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參數(shù)資料
| 型號： | M378T6453FZ3-CD5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 40 Characters x 4 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 無緩沖DDR2的內(nèi)存模塊 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 382K |
| 代理商： | M378T6453FZ3-CD5 |
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Input/Output Functional Description
Symbol
Type
Function
CK0-CK2
CK0-CK2
Input
CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge of
CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing)
CKE0-CKE1
Input
Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks, CKE
low initiates the Powe Down mode, or the Self-Refresh mode
S0-S1
Input
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the
command decoder is disbled, new command are ignored but previous operations continue. This signal provides for exter-
nal rank selection on systems with multiple ranks
RAS, CAS, WE
Input
RAS, CAS, and WE (
ALONG WITH
CS) define the command being entered.
ODT0-ODT1
Input
When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the
Extended Mode Register Set (EMRS).
V
REF
Supply
Reference voltage for SSTL 18 inputs.
V
DDQ
Supply
Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered
DIMM designs, VDDQ shares the same power plane as VDD pins.
BA0-BA1
Input
Selects which SDRAM BANK of four is activated.
A0-A13
Input
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the colum address, In addition to the column address, AP
is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge
command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to pre-
charge.
DQ0-DQ63
CB0-CB7
In/Out
Data and Check Bit Input/Output pins.
DM0-DM8
Input
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data
during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading.
V
DD
,V
SS
Supply
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to V
DD
/V
DDQ
planes on
these modules.
DQS0-DQS8
DQS0-DQS8
In/Out
Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the
DRAMs and DQ8-17 connect to the UDQS pin of the DRAM
SA0-SA2
Input
These signals and tied at the system planar to either V
SS
or V
DD
to configure the serial SPD EERPOM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the
SDA bus line to VDD to act as a pullup on the system board.
SDA
In/Out
SCL
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to VDD to act as a pullup onthe system board.
V
DD
SPD
Supply
Power supply for SPD EEPROM. This supply is separate from the V
DD
/V
DDQ
power plane. EEPROM supply is operable
from 1.7V to 3.6V.
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