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參數(shù)資料
| 型號： | M378T3253FG0-CD5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR2 Unbuffered SDRAM MODULE |
| 中文描述： | 無緩沖DDR2的內(nèi)存模塊 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 382K |
| 代理商： | M378T3253FG0-CD5 |
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Operating Temperature Condition
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 0 - 85
°
C, operation temperature range are the temperature which all DRAM specification will be supported.
3. At 85 - 95
°
C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Input AC Logic Level
AC Input Test Conditions
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
IH/IL
(AC)
level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from V
REF
to V
IH
(AC) min for rising edges and the range from V
REF
to V
IL
(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from V
IL
(AC) to V
IH
(AC) on the positive transitions and V
IH
(AC) to V
IL
(AC) on the negative
transitions.
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°
C
1, 2, 3
Symbol
Parameter
Min.
Max.
Units
Notes
V
IH
(DC)
V
IL
(DC)
DC input logic high
V
REF
+ 0.125
V
DDQ
- 0.3
V
DDQ
+ 0.3
V
REF
- 0.125
V
DC input logic low
V
Symbol
Parameter
DDR2-400, DDR2-533
DDR2-667
Units
Notes
Min.
Max.
Min.
Max.
V
IH
(AC)
V
IL
(AC)
AC input logic high
V
REF
+ 0.250
-
-
V
REF
+ 0.200
V
AC input logic low
V
REF
- 0.250
V
REF
- 0.200
V
Symbol
Condition
Value
Units
Notes
V
REF
Input reference voltage
0.5 * V
DDQ
1.0
V
1
V
SWING(MAX)
SLEW
Input signal maximum peak to peak swing
V
1
Input signal minimum slew rate
1.0
V/ns
2, 3
V
DDQ
V
IH
(AC) min
V
IH
(DC) min
V
REF
V
IL
(DC) max
V
IL
(AC) max
V
SS
< AC Input Test Signal Waveform >
V
SWING(MAX)
delta TR
delta TF
V
REF
- V
IL
(AC) max
delta TF
Falling Slew =
Rising Slew =
V
IH
(AC) min - V
REF
delta TR
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| M378T3253FG0-CE6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE |
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| M378T3253FG3-CD5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE |
| M378T3253FG3-CE6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE |
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