參數(shù)資料
型號： M37754S4CHP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 5/115頁
文件大小： 1571K
代理商： M37754S4CHP
101
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
× 109
f(XIN)
7
× 109
f(XIN)
4
× 109
f(XIN)
3
× 109
f(XIN)
3
× 109
f(XIN)
2
× 109
f(XIN)
3
× 109
f(XIN)
3
× 109
f(XIN)
2
× 109
f(XIN)
3
× 109
f(XIN)
3
× 109
f(XIN)
2
× 109
f(XIN)
2
× 109
f(XIN)
5
× 109
f(XIN)
5
× 109
f(XIN)
1
× 109
f(XIN)
3
× 109
f(XIN)
2
× 109
f(XIN)
2
× 109
f(XIN)
1
× 109
f(XIN)
2
× 109
f(XIN)
2
× 109
f(XIN)
1
× 109
f(XIN)
2
× 109
f(XIN)
2
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
5
× 109
f(XIN)
2
× 109
f(XIN)
2
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
1
× 109
f(XIN)
tsu(A–DL/DH)
tsu(CS–DL/DH)
tw(
φH), tw(φL)
__
tw(WR), tw(RD)
td(A–WR)
td(A–RD)
td(A–ALE)
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
tw(ALE)
th(WR–A)
th(RD–A)
td(WR–BHE)
td(RD–BHE)
td(WR–CS)
td(RD–CS)
th(WR–DLQ/DHQ)
tpxz(WR–DLZ/DHZ)
tsu(LA–DL)
td(LA–WR)
td(LA–RD)
td(LA–ALE)
td(ALE–LA)
tpzx(RD–DLZ)
Symbol
Data setup time with address stabilized
Data setup time with chip select stabilized
φ high-level pulse width, φ low-level pulse width
___ ___
WR, RD low-level pulse width
Address output delay time
____
BHE outuput delay time
____
BHE outuput delay time
____
BHE outuput delay time
Chip select output delay time
ALE pulse width
Address hold time
____
BHE hold time
____
BHE hold time
Chip select hold time
Data hold time
Floating start delay time
Data setup time with address stabilized
Address outuput delay time
Address hold time
Floating release delay time
Parameter
3-
φ access
4-
φ access
Unit
5-
φ access
ns
– 60
– 20
– 25
– 15
– 25
– 15
– 25
– 15
– 10
+ 5
– 75
– 35
– 20
– 15
– 10
– 65
– 20
– 30
– 15
– 30
– 15
– 30
– 15
9
× 109
f(XIN)
9
× 109
f(XIN)
6
× 109
f(XIN)
– 65
– 20
Bus timing data formulas
Memory expansion and Microprocessor mode : High-speed running (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN)
≤ 40 MHz when
the clock source select bit = “0”, unless otherwise noted)
7
× 109
f(XIN)
3
× 109
f(XIN)
3
× 109
f(XIN)
2
× 109
f(XIN)
– 75
– 35
– 20
V: f(XIN)
≤ 20 MHz when the clock source select bit = “1”
Note: When the clock source select bit is “1”, regard f(XIN) in tables as 2f(XIN).
9
× 109
f(XIN)
– 75
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