參數(shù)資料
型號： M37754S4CHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
中文描述： 單芯片16位微機的CMOS
文件頁數(shù)： 53/114頁
文件大小： 1116K
代理商： M37754S4CHP
53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ASYNCHRONOUS
SERIAL COMMUNICATION
Asynchronous serial communication can be performed using 7-, 8-,
or 9-bit length data. The operation is the same for all data lengths.
The following is the description for 8-bit asynchronous communica-
tion.
With 8-bit asynchronous communication, bit 0 of UARTi Transmit/
Receive mode register is “1”, bit 1 is “0”, and bit 2 is “1”.
Bit 3 is used to select an internal clock or an external clock. If bit 3 is
“0”, an internal clock is selected and if bit 3 is “1”, then external clock
is selected. If an internal clock is selected, bit 0 (TCS
0
) and bit 1
(TCS
1
) of UARTi Transmit/Receive control register 0 are used to se-
lect the clock source. When an internal clock is selected for asyn-
chronous serial communication, the CLKi pin can be used as a
normal I/O pin.
The selected internal or external clock is divided by (n+1), then by
16, and is passed through a control circuit to create the UART trans-
mission clock or UART receive clock.
Therefore, the transmission speed can be changed by changing the
contents (n) of the bit rate generator. If the selected clock is an inter-
nal clock Pfi or an external clock f
EXT
,
Bit Rate = (Pfi or f
EXT
) / {(n+1)
×
16}
Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits.
Bit 5 is a select bit of odd parity or even parity.
In the odd parity mode, the parity bit is adjusted so that the sum of 1s
in the data and parity bit is always odd.
In the even parity mode, the parity bit is adjusted so that the sum of
the 1s in the data and parity bit is always even.
Bit 6 is the parity bit select bit which indicates whether to add parity
bit or not.
Bits 4 to 6 must be set or reset according to the data format used in
the communicating devices.
Bit 7 is the sleep select bit. The sleep mode is described later.
The UARTi Transmit/Receive control register 0 bit 2 is used to deter-
____
If CTSi input is selected, the user can control whether to stop or start
transmission by external CTSi input.
Bit 4 of the UART Transmit/Receive control register 0 is used to de-
____
____
nal is not used. When CTS or RTS signal is not used, CTS/RTS pin
can be used as a normal port. The case using CTS and RTS signals
are explained below. However, when CTS and RTS signals are not
used, there are no condition of CTSi input, and there is no RTSi out-
put.
Clear UARTj Transmit/Receive control register 0 bit 7 to “1” in asyn-
chronous communication.
____
___
___
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