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參數資料
| 型號： | M3773S4L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 16 Bits CMOS Microcomputer(16位單片機) |
| 中文描述： | 單片微機16位的CMOS（16位單片機） |
| 文件頁數： | 13/36頁 |
| 文件大小： | 927K |
| 代理商： | M3773S4L |
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13
MITSUBISHI MICROCOMPUTERS
M37733S4LHP
16-BIT CMOS MICROCOMPUTER
New product
____
HLDA
is a hold acknowledge signal and is used to notify externally
HOLD
input and enters hold state.
HOLD
is a hold request signal. It is an input signal used to put the
microcomputer in hold state.
HOLD
input is accepted when the internal
clock
falls from “H” level to “L” level while the bus is not used.
P0
0
/A
0
to P0
7
/A
7
pins, P1
0
/A
8
/D
8
to P1
15
/D
15
pins, P2
0
/A
16
/D
0
to
P2
7
/A
23
/D
7
pins, P3
0
/R/
W
pin, and P3
1
/
BHE
pin are floating while the
microcomputer stays in hold state. These pins are floating after one
cycle of the internal clock
later than
HLDA
signal changes to “L”
level. At the removing of hold state, these ports are removed from
floating state after one cycle of internal clock
___
RDY
is a ready signal. If this signal goes “L”, the internal clock
stops at “L”.
RDY
is used when slow external memory is attached.
P4
2
/
independent of
RDY
and does not stop even when internal clock
stops because of “L” input to the
RDY
pin. As shown in Table 2,
output can also be stopped with the signal output disable selection
bit “1”. In this case, write “1” to the port P4
2
direction register.
___
later than
HLDA
signal
1
pin is an output pin for clock
1
. The
1
output is
1
(2) Evaluation chip mode [11]
Evaluation chip mode is entered by applying voltage twice the V
CC
voltage to the CNV
SS
pin. This mode is normally used for evaluation
tools.
_
The functions of
E
, P0
0
/A
0
to P0
7
/A
7
pins, R/
W
,
BHE
, ALE, and
HLDA
are the same as those in microprocessor mode.
P1
0
/A
8
/D
8
to P1
7
/A
15
/D
15
pins function as address output pins while
_
E
is “H” and as data I/O pin of odd addresses while
E
is “L” regardless
of the BYTE pin level. However, if an internal memory is read, external
data is ignored while
E
is “L”. P2
0
/A
16
/D
0
to P2
7
/A
23
/D
7
pins function
_
as address output pins while
E
is “H” and as data I/O pin of even
addresses while
E
is “L” when the BYTE pin level is “L”. However, if
an internal memory is read, external data is ignored while
E
is “L”.
When the BYTE pin level is “H” or 2V
CC
, port P2 functions as an
address output pin while
E
is “H” and as data I/O pin of even and odd
addresses while
E
is “L”. However, if an internal memory is read,
external data is ignored while
E
is “L”.
Port P4 and its data direction which are located at address 0A
16
and
0C
16
are treated differently in evaluation chip mode. When these
_
___
____
addresses are accessed, the data bus width is treated as 16 bits
regardless of the BYTE pin level, and the access cycle is treated as
internal memory regardless of the wait bit.
The functions of
HOLD
and
RDY
are the same as those in
microprocessor mode. Clock
regardless of signal output disable selection bit.
Ports P4
3
to P4
6
become MX, QCL, VDA, and VPA output pins
respectively. Port P4
7
becomes the
DBC
input pin.
The MX signal normally contents of flag m, but the contents of flag x
is output if the CPU is using flag x.
QCL is the queue buffer clear signal. It becomes “H” when the
instruction queue buffer is cleared, for example, when a jump
instruction is executed.
VDA is the valid data address signal. It becomes “H” while the CPU
is reading data from data buffer or writing data to data buffer. It also
becomes “H” when the first byte of the instruction (operation code) is
read from the instruction queue buffer.
VPA is the valid program address signal. It becomes “H” while the
DBC
is the debug control signal and is used for debugging. Table 1
shows the relationship between the CNV
SS
pin input levels and
processor modes.
1
from P4
2
/
1
pin is always output
Table 1. Relationship between CNVss pin input levels and processor
modes
CNVss
Mode
Microprocessor
( Evaluation chip)
2 Vcc
Evaluation chip
Description
Vss
Microprocessor mode upon
starting after reset.
Evaluation chip mode only.
_
E
_
E
is output when the internal/external memory
area is accessed.
After WIT/STP instruction is executed,
“H” is output.
_
E
is output only when the external memory
area is accessed.
“L” is output after WIT/STP instruction is
executed.
Standby state selection bit (bit 0 of port
function control register) must be set to “1”.
“H”or “L” is output. (Output the content of
P4
2
latch.)
Port P4
2
direction register must be set to
“1”.
Microprocessor mode
1
Clock
1
is output.
Table 2. Function of signal output disable selection bit CM
6
(bit 6 of oscillation circuit control register 0)
Function
CM
6
= “0”
CM
6
= “1”
Processor mode
Pin
Note.
Functions shown in Table 2 cannot be emulated in a debugger.
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