參數(shù)資料
型號(hào): M37736EHBGS
廠商: Mitsubishi Electric Corporation
英文描述: PROM VERSION OF M37736EHBXXXGP
中文描述: PROM的版本M37736EHBXXXGP
文件頁數(shù): 10/96頁
文件大?。?/td> 1328K
代理商: M37736EHBGS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
10
Port P2
E
ALE
Port P2
E
ALE
Internal clock
Internal clock
Port P2
E
ALE
A
D
A
D
A
D
A + 1
D
A
D
A + 1
D
A
D
A + 1
D
(1)
(2)
(3)
(4)
(5)
(6)
Access time
Access time
Access time
Access time
Access time
Access time
A
D
D
A +
1
A
D
A
D
A + 1
D
(7)
(8)
(9)
(10)
Access time
Access time
D
A
A + 1
D
A
D
A + 1
D
Access time
Access time
A : Address
D : Data
Port P2
E
ALE
Port P2
E
ALE
Port P2
E
ALE
Port P2
E
ALE
Port P2
E
ALE
Port P2
E
ALE
Port P2
E
ALE
The bus interface unit operates using one of the waveforms (1) to
(10) shown in Figure 5. The standard waveforms are (1) and (2).
The ALE signal is used to latch only the address signal from the
multiplexed signal containing data and address.
S
ignal
E
becomes “L” when the bus interface unit reads an instruction
code or data from the memory or when it writes data to the memory.
Whether to perform read or write is controlled by signal R/
W
. When
signal R/
W
is “H”, read is performed; when “L”, write is performed.
In the external bus mode B, signals
E
and R/
W
are not directly output
to the outside of the chip. In the memory expansion mode or the
microprocessor mode, read signal
RDE
and write signals
WEL
,
WEH
are output to the outside of the chip. While signal
E
is “L”, signal
becomes “L” at reading. While signal
E
is “L”, signals
WEL
and
WEH
become “L” at writing.
___
Waveform (1) in Figure 5 is used to access a single byte or two bytes
simultaneously. To read or write two bytes simultaneously, the first
address accessed must be even. Furthermore, when accessing an
external memory area in the memory expansion mode or the
microprocessor mode, set the bus width selection input pin (BYTE)
to “L” (external data bus has a width of 16 bits). The data bus in the
internal memory area is always treated as the 16-bit bus independent
of BYTE.
Fig. 5 Bus access timing
_
___
While signal
E
is “L” in the external bus mode B, signal
becomes “L” (in the read cycle) or signals
WEL
and
WEH
become “L” (in the write cycle).
____
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