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參數資料
| 型號： | M37735MHLXXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數： | 28/28頁 |
| 文件大?。?/td> | 789K |
| 代理商： | M37735MHLXXXHP |
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8
MITSUBISHI MICROCOMPUTERS
M37735MHLXXXHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
VCC = 5 V,
f(XIN) = 12 MHz (square waveform),
(f(f2) = 6 MHz),
f(XCIN) = 32.768 kHz,
in operating (Note 1)
VCC = 3 V,
f(XIN) = 12 MHz (square waveform),
(f(f2) = 6 MHz),
f(XCIN) = 32.768 kHz,
in operating (Note 1)
VCC = 3 V,
f(XIN) = 12 MHz (square waveform),
(f(f2) = 0.75 MHz),
f(XCIN) : Stopped,
in operating
VCC = 3 V,
f(XIN) = 12 MHz (square waveform),
f(XCIN) = 32.768 kHz,
when a WIT instruction is executed (Note 2)
VCC = 3 V,
f(XIN) : Stopped,
f(XCIN) = 32.768 kHz,
in operating (Note 3)
VCC = 3 V,
f(XIN) : Stopped,
f(XCIN) = 32.768 kHz,
when a WIT instruction is executed (Note 4)
Ta = 25
°C,
when clock is stopped
Ta = 85
°C,
when clock is stopped
mA
A
Max.
9
6
0.8
12
60
6
1
20
Limits
Typ.
4.5
3
0.4
6
30
3
Unit
Min.
Test conditions
Symbol
Parameter
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85
°C, unless otherwise noted)
When single-chip
mode, output pins
are open, and
other pins are VSS.
Power source
current
ICC
Limits
Min.
Typ.
Max.
—
Resolution
VREF = VCC
10
Bits
—
Absolute accuracy
VREF = VCC
± 3
LSB
RLADDER
Ladder resistance
VREF = VCC
10
25
k
tCONV
Conversion time
19.6
s
VREF
Reference voltage
2.7
VCC
V
VIA
Analog input voltage
0
VREF
V
Symbol
Parameter
Test conditions
Unit
A–D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –40 to +85
°C, f(XIN) = 12 MHz, unless otherwise noted (Note))
Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz.
Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop
bit = “1”.
2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.
3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.
4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.
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