參數(shù)資料
型號(hào)： M37641M8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 57/149頁
文件大?。?/td> 1997K
代理商： M37641M8
57
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
[USB endpoint x (x = 0 to 4) OUT Write Count Registers (Low
and High)] WRT_CNTRL, WRT_CNTH
These registers contain the number of bytes in the endpoint x
OUT FIFO. These are read-only registers. These two registers
must be read after the USB FCU has received a packet of data
from the host. When reading these registers, the lower byte must
be read first, then the higher byte.
When the OUT FIF0 is in double buffer mode, the CPU first reads
the received number of bytes of the former data packet. The next
CPU read can obtain that of the new data packet.
Fig. 51 Structure of USB endpoint x (x = 0 to 4) OUT write count registers
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USB endpoint x OUT write count register High (address 005E
16
)
WRT_CNTH
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7
[USB Endpoint x (x = 0 to 4) FIFO Register] USBFIFOx
These registers are the USB IN (transmit) and OUT (receive) FIFO
data registers. Write data to the corresponding register, and read
data from the corresponding register.
When the maximum packet size is equal to or less than half the
FIFO size, these registers function in double buffer mode and can
hold two packets of data. When the IN_PKT_RDY bit is
“
0
”
and
the TX_NOT_EMPTY bit is
“
1
”
, these bits indicate that one packet
of data is stored in the IN FIFO. When the OUT FIFO is in double
buffer mode, the OUT_PKT_RDY flag remains as
“
1
”
after the first
packet of data is read out (it actually goes to
“
0
”
and returns to
“
1
”
after one
φ
cycle).
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O
USB endpoint x FIFO register
(addresses 0060
16
, 0061
16
, 0062
16
, 0063
16
, 0064
16
,)
USBFIFOx
b0
b
7
Fig. 52 Structure of USB endpoint x (x = 0 to 4) FIFO register
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