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參數(shù)資料
| 型號： | M37640M8-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE CHIP 8 BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片微機(jī)8位CMOS |
| 文件頁數(shù)： | 60/96頁 |
| 文件大?。?/td> | 1477K |
| 代理商： | M37640M8-XXXFP |
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60
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
All of the conditions stated on the preceeding page
(except the bad data toggle in the SETUP state case)
cause the device to send a STALL handshake for the
IN/OUT token in question. In the bad data toggle in
the SETUP stage case, the device sends ACK for the
SETUP stage and then sends STALL for the next IN/
OUT token. A STALL handshake caused by the
above conditions lasts for only one transaction and
terminates the ongoing control transfer. Any packet
after the STALL handshake will be seen as the begin-
ning of a new control transfer.
The CPU writes a “0” to clear this FORCE_STALL
status bit.
IN0CSR5 (SETUP_END):
The USB FCU sets this bit
to a “1” if a control transfer has ended before the spe-
cific length of data is transferred during the data
phase. The CPU clears this bit by way of writing a “1”
to IN0CSR7. Once the CPU sees the SETUP_END
bit set, it should stop accessing the FIFO to service
the previous setup transaction. If OUT_PKT_RDY is
set at the same time that SETUP_END is set, it indi-
cates that the previous setup transaction ended and a
new SETUP token is in the FIFO.
IN0CSR6 and IN0CSR7:
These bits are used to clear
IN0CSR0 and IN0CSR5 respectively. Writing a “1” to
these bits will clear the corresponding register bit.
The
USB Endpoint x IN CSR
, shown in Figure 1.63,
contains control and status information of the respec-
tive IN endpoint 1-4. The USB Endpoint Index Register
selects the specific endpoint.
INXCSR0
(IN_PKT_RDY)
(TX_FIFO_NOT_EMPTY):
These two bits are read
together to determine IN FIFO status. A “1” can be
written to the INXCSR0 bit by the CPU to indicate a
packet of data is written to the FIFO (See Chapter.
for detail).
INXCSR1 (UNDER_RUN):
This bit is used in ISO
mode only to indicate to the CPU that a FIFO
underrun has occurred. The USB FCU sets this bit to
a “1” at the beginning of an IN token if no data packet
is in the FIFO. Setting this bit will cause the INST12
bit of the Interrupt Status Register 2 to set. The CPU
writes a “0” to clear this bit.
INXCSR2 (SEND_STALL):
The CPU writes a “1” to
this bit when the endpoint is stalled (transmitter halt).
The USB FCU returns a STALL handshake while this
bit is set. The CPU writes a “0” to clear this bit.
and
INXCSR5
Fig. 1.63. USB Endpoint x IN CSR (IN_CSR)
INXCSR7
INXCSR5
INXCSR4
INXCSR3
INXCSR2
INXCSR1
INXCSR0
MSB
7
LSB
0
INXCSR6
Address: 0059
16
Access: R/W
Reset: 00
16
INXCSR0
IN_PKT_RDY Bit (bit 0)(Write "1" only or Read)
0: In packet is not ready
1: In packet is ready
UNDER_RUN Flag (bit 1)(Write "0" only or Read)
0: No FIFO underrun
1: FIFO underrun has occurred
SEND_STALL Bit (bit 2)
0: No action
1: Stall IN Endpoint X by the CPU
ISO/TOGGLE_INIT Bit (bit 3)
0: Select non-isochronous transfer (0->1->0) reset data toggle to DATA0
1: Select isochronous transfer
INTPT Bit (bit 4)
0: Select non-rate feedback interrupt transfer
1: Select rate feedback interrupt transfer
TX_NOT_EPT Flag (bit 5) (Read Only - Write "0")
0: Transmit FIFO is empty
1: Transmit FIFO is not empty
FLUSH Bit (bit 6) (Write Only - Read "0")
0: No action
1: Flush the FIFO
AUTO_SET Bit (bit 7)
0: AUTO_SET disabled
1: AUTO_SET enabled
INXCSR1
INXCSR2
INXCSR3
INXCSR4
INXCSR5
INXCSR6
INXCSR7
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