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參數(shù)資料
| 型號： | M37640M8-126FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 65/96頁 |
| 文件大?。?/td> | 1477K |
| 代理商： | M37640M8-126FP |
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65
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data Bus
I
O
U
7
U
6
U
5
U
4
A
00
U
2
IBF
0
b
7
b
0
System Bus
OBF
0
b
1
b
0
D
OBF
0
IBF
0
A
0
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
S
0
R
W
RD
WR
DBB
0
DBBS
0
I
O
U
7
U
6
U
5
U
4
A
01
U
2
IBF
1
b
7
b
0
OBF
1
b
1
b
0
D
OBF
1
IBF
1
A
0
S
1
R
W
RD
WR
1
DBBS
1
Fig. 1.75. Bus Interface Circuit
Fig. 1.76. Data Bus Buffer Interrupt Request Circuit
One-shot pulse
One-shot pulse
One-shot pulse
One-shot pulse
Rising Edge
Rising Edge
Rising Edge
Rising Edge
Input Buffer full interrupt
request signal IBF
Output Buffer Empty interrupt
request signal OBE
Input buffer full flag 0
IBF0
Input buffer full flag 1
IBF1
Output buffer fullOBF0
Output buffer full flag 1
OBF1
Set interrupt request at this rising edge
Set interrupt request at this rising edge
IBF0
IBF1
IBF
(OBF1
OBE
(OBF0
1.22 MASTER CPU BUS INTERFACE
This device has a bus interface function with 2 I/O buff-
ers that can be operated in slave mode by control
signals from the master CPU (see Figure 1.75). Bus
Interface Circuit). The bus interface can be connected
directly to either a R/W type of CPU or a CPU with RD
and WR separate signals. Slave mode is selected
with the bit 7 of the data buffer control register 0. The
single data bus buffer mode and the double data bus
buffer mode are selected with bit 7 of the Data Bus
Buffer Control register 1. When selecting the double
data bus buffer mode, Port P72 becomes S
1
input.
Prior to enabling the MBI, Port 6 must be placed in in-
put mode by writing 00
16
to P6D (0015
16
).
When data is written to the MCU from the master
CPU, an input buffer full interrupt request occurs.
Similarly, when data is read from the master CPU, an
output buffer empty interrupt request occurs.
When the bus interface is operating, DQ
0
-DQ
7
be-
come a 3-state data bus that sends and receives
data, command, and status to and from the master
CPU. At the same time, W, R, S
0
, S
1
, and A
0
become
host CPU control signal input pins.
The two input buffer full interrupt requests and two out-
put buffer full requests are multiplexed as shown in
Figure 1.76.
The bus interface can be operated under normal
MCU control or under on-chip DMA control for fast
data transfer. If a master CPU has a large amount of
data to be transferred, use of the on-chip DMA con-
troller is highly recommended.
The bus interface signal input level can be pro-
grammed as CMOS level (default) or as TTL level.
Bit7 of the Port Control Register (PTC
7
) is used for the
input level selection.
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