參數(shù)資料
型號: M37640E8FS
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 77/96頁
文件大?。?/td> 1477K
代理商: M37640E8FS
77
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.25 LOW POWER MODES
This device has two low-power dissipation modes:
Stop
Wait
1.25.1 Stop Mode
Use of the stop mode allows the MCU to be placed in
a state where no internal excitation of the circuitry is
taking place, thus resulting in extremely low power
dissipation. The MCU enters the stop mode when the
STP instruction is executed. The internal state of the
mcu after execution of the STP instruction is as fol-
lows:
Timer 1 and Timer 2 are loaded with FF
16
and 01
16
respectively.
All T123M mode register bits are reset to their default
value except bit 4.
The count source for Timer 1 is set to /8 and the
count source for Timer 2 is set to Timer 1 underflow.
Oscillation is restarted when a reset or an external in-
terrupt is received. The interrupt control bit of the
interrupt used to release the stop mode must be set
to a "1" and the I flag set to a "0" prior to the execution
of the STP instruction. To allow the oscillation source
time to stabilize, the oscillation source is connected
as the clock source for the wake-up timer (Timer 1
and Timer 2 cascaded). When Timer 2 underflows,
the MCU services the interrupt that caused the return
from the stop state. Afterwards, it services any other
enabled interrupts that occurred, in the order of their
respective priorities, and returns to its state prior to
the execution of the STP instruction. The timing for
the STP instruction is shown in Figure 1.97.
Fig. 1.97. STP Cycle Timing Diagram (STP)
Φ
out
SYNC
out
RD
WR
Address
Data
Opcode
Invalid
S,CPMA2
PC + 1
PC
X
in
INTREQ
STPSIG
CPUOSC
(PC + 1)H
Sleep Period
Timer Countdown
(Oscillator stabilization)
Timer 2 underflow
Start of Interrupt Service
Routine
ote:
Return from a STP Instruction is caused by an interrupt, followed by the countdown and underflow of Time 2
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