參數(shù)資料
型號: M37548G2FP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20
封裝: 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20
文件頁數(shù): 57/86頁
文件大?。?/td> 1437K
代理商: M37548G2FP
Rev.2.02
Mar 31, 2009
Page 58 of 81
REJ03B0210-0202
7548 Group
NOTES ON USE
Countermeasures against noise
It is necessary not only design the system taking measures
against the noise as follows but to evaluate before actual use.
1. Shortest wiring length
(1) Package
Select the smallest possible package to make the total wiring
length short.
<Reason>
The wiring length depends on a microcomputer package. Use of
a small package, for example QFP and not DIP, makes the total
wiring length short to reduce influence of noise.
Fig 73. Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20 mm).
<Reason>
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is
completely initialized. This may cause a program runaway.
Fig 74. Wiring for the RESET pin
(3) Wiring for clock input/output pins
Make the length of wiring which is connected to clock I/O
pins as short as possible.
Make the length of wiring (within 20 mm) across the
grounding lead of a capacitor which is connected to an
oscillator and the VSS pin of a microcomputer as short as
possible.
Separate the VSS pattern only for oscillation from other
VSS patterns.
<Reason>
If noise enters clock I/O pins, clock waveforms may be
deformed. This may cause a program failure or program
runaway. Also, if a potential difference is caused by the noise
between the VSS level of a microcomputer and the VSS level of
an oscillator, the correct clock will not be input in the
microcomputer.
Fig 75. Wiring for clock I/O pins
(4) Wiring to CNVSS pin
Connect CNVSS pin to a GND pattern at the shortest distance.
The GND pattern is required to be as close as possible to the
GND supplied to VSS.
In order to improve the noise reduction, to connect a 5 k
resistor serially to the CNVSS pin - GND line may be valid.
As well as the above-mentioned, in this case, connect to a GND
pattern at the shortest distance. The GND pattern is required to
be as close as possible to the GND supplied to VSS.
<Reason>
The CNVSS pin of the QzROM is the power source input pin for
the built-in QzROM. When programming in the built-in
QzROM, the impedance of the CNVSS pin is low to allow the
electric current for writing flow into the QzROM. Because of
this, noise can enter easily. If noise enters the CNVSS pin,
abnormal instruction codes or data are read from the built-in
QzROM, which may cause a program runaway.
Fig 76. Wiring for the VPP pin of the QzROM
DIP
SDIP
SOP
QFP
RESET
Reset
circuit
Noise
VSS
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Noise
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
O.K.
CNVSS
VSS
About 5 k
The shortest
(Note)
Note: This indicates pin.
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