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| 型號(hào)： | M37544G2ASP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 28 X 8.90 MM, 1.78 MM PITCH, PLASTIC, SDIP-32 |
| 文件頁(yè)數(shù)： | 17/75頁(yè) |
| 文件大?。?/td> | 649K |
| 代理商： | M37544G2ASP |
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7544 Group (QzROM version)
REJ03B0108-0103
Rev.1.03
Mar 31, 2009
page 24 of 72
Fig. 21 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
Fig. 20 Interrupt sequence
φ
SYNC
RD
WR
Address bus
Data bus
PC
Not used
S,SPS
S-1,SPS S-2,SPS
BL
BH
AL,AH
PCH
PCL
PS
AL
AH
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS
: “0016” or “0116”
([SPS] is a page selected by the stack page selection bit of CPU mode register.)
Push onto stack
Vector fetch
Execute interrupt
routine
Instruction cycle
Push onto stack
Vector fetch
Instruction cycle
Internal clock φ
SYNC
T1
IR1 T2
IR2 T3
T1 T2 T3 : Interrupt acceptance timing points
IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.
Note : Period 2 indicates the last φ cycle during one instruction cycle.
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt
requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2
separately.
■ Notes on Interrupts
When setting the followings, the interrupt request bit of the corre-
sponding interrupt may be set to “1”.
<When switching external interrupt active edge>
INT0 interrupt edge selection bit
(bit 0 of Interrupt edge selection register (address 003A16))
INT1 interrupt edge selection bit
(bit 1 of Interrupt edge selection register)
CNTR0 active edge switch bit
(bit 2 of timer X mode register (address 002B16))
CNTR1 active edge switch bit
(bit 6 of timer A mode register (address 100D16))
If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1) Set the corresponding enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit (the active edge switch bit)
or the interrupt source bit.
(3) Set the corresponding interrupt request bit to “0” after one or
more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
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