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參數(shù)資料
| 型號： | M37542M4-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQCC36 |
| 封裝： | 6 X 6 MM, 0.50 MM PITCH, PLASTIC, WQFN-36 |
| 文件頁數(shù)： | 97/122頁 |
| 文件大?。?/td> | 1311K |
| 代理商： | M37542M4-XXXHP |
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7542 Group
Rev.3.03
Jul 11, 2008
Page 76 of 117
REJ03B0006-0303
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: Effective only when the suspend enable bit = “1”.
b7
b0
Erase Suspend enble bit (Notes 1)
0 : Suspend invalid
1 : Suspend valid
Erase Suspend
request bit (Notes 2)
0 : Erase restart
1 : Suspend request
Erase Suspend flag
0 :
Erase active
1 :
Erase inactive (Erase Suspend mode)
Not used (do not write “1” to this bit.)
Flash memory control register 1
(FMCR1: address : 0FE116: initial value: 4016)
Figure 99 shows the flash memory control register 1.
Bit 0 of the flash memory control register 1 is the Erase suspend
enable bit. By setting this bit to “1”, the erase suspend mode to
suspend erase processing temporarily when block erase com-
mand is executed can be used. In order to set this bit to “1”,
writing “0” and “1” in succession to bit 0. In order to set this bit to
“0”, write “0” only to bit 0.
Bit 1 of the flash memory control register 1 is the erase suspend
request bit. By setting this bit to “1” when erase suspend enable
bit is “1”, the erase processing is suspended.
Bit 6 of the flash memory control register 1 is the erase suspend
flag. This bit is cleared to “0” at the flash erasing.
Figure 100 shows the flash memory control register 2.
Bit 0 of the flash memory control register 1 is the all user block E/
W enable bit. By setting this bit to “0”, Erase/Write to all user block
(blocks 0, 1, 2) is disabled. As a result, error writing in program to
write only to data block can be prevented.
Fig. 99 Structure of flash memory control register 1
Fig. 100 Structure of flash memory control register 2
Table 10 Erase/Write disable setting
CPU rewrite
mode select bit
0
1
All user block
E/W enable bit
0
1
0
1
8KB user block
E/W enable bit
0
1
0
1
0
1
0
1
Block 0: 8KB
Block 1: 8KB
E/W disabled (RESET)
E/W disabled
E/W enabled
Block 2: 16KB
E/W disabled (RESET)
E/W disabled
E/W enabled
Data block A: 2KB
Data block B: 2KB
E/W disabled (RESET)
E/W disabled
E/W enabled
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: Effective only when the CPU rewrite mode select bit = “1”.
b7
b0
Reserved bit (returns “1” when read)
Reserved bits (do not write “1” to this bit.)
All user block E/W enable
bit (Notes 1, 2)
0 : E/W disabled
1 : E/W enabled
Not used (do not write “1” to this bit.)
Flash memory control register 2
(FMCR2: address : 0FE216: initial value: 0116)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
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| M37544G2AGP#U0 | 功能描述:IC 740 MCU OTP 8K 32LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產品培訓模塊:MCU Product Line Introduction AVR® UC3 Introduction 標準包裝:2,500 系列:AVR®32 UC3 B 核心處理器:AVR 芯體尺寸:32-位 速度:60MHz 連通性:I²C，IrDA，SPI，SSC，UART/USART，USB 外圍設備:欠壓檢測/復位，DMA，POR，PWM，WDT 輸入/輸出數(shù):28 程序存儲器容量:128KB（128K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.65 V ~ 1.95 V 數(shù)據轉換器:A/D 6x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TQFP 包裝:帶卷 (TR) 配用:ATSTK600-TQFP48-ND - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1101-ND - KIT DEV/EVAL FOR AVR32 AT32UC3B 其它名稱:AT32UC3B1128-AUR-NDAT32UC3B1128-AURTR |
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