參數(shù)資料
型號： M37542M2-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 8.9 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù)： 9/124頁
文件大小： 1238K
代理商： M37542M2-XXXSP
7542 Group
Rev.3.03
Jul 11, 2008
Page 104 of 117
REJ03B0006-0303
Switching Characteristics
Table 25 Switching characteristics (1)
(FLASH ROM version: VCC = 4.0 to 5.5V, Mask ROM version: VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
tC(SCLK1)/2–30
–30
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tr(CMOS)
tf(CMOS)
Serial I/O1, serial I/O2 clock output “H” pulse width
Serial I/O1, serial I/O2 clock output “L” pulse width
Serial I/O1, serial I/O2 output delay time
Serial I/O1, serial I/O2 output valid time
Serial I/O1, serial I/O2 clock output rising time
Serial I/O1, serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Note 1: Pin XOUT is excluded.
Table 26 Switching characteristics (2)
(FLASH ROM version: VCC = 2.7 to 5.5V, Mask ROM version: VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
350
50
Note 1: Pin XOUT is excluded.
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tr(CMOS)
tf(CMOS)
Serial I/O1, serial I/O2 clock output “H” pulse width
Serial I/O1, serial I/O2 clock output “L” pulse width
Serial I/O1, serial I/O2 output delay time
Serial I/O1, serial I/O2 output valid time
Serial I/O1, serial I/O2 clock output rising time
Serial I/O1, serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
tC(SCLK1)/2–50
–30
20
ns
10
140
30
ns
Table 27 Switching characteristics (3)
(VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
450
70
Note 1: Pin XOUT is excluded.
Switching characteristics measurement circuit diagram
/ / /
Measured
output pin
CMOS output
100 pF
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tr(CMOS)
tf(CMOS)
Serial I/O1, serial I/O2 clock output “H” pulse width
Serial I/O1, serial I/O2 clock output “L” pulse width
Serial I/O1, serial I/O2 output delay time
Serial I/O1, serial I/O2 output valid time
Serial I/O1, serial I/O2 clock output rising time
Serial I/O1, serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
tC(SCLK1)/2–70
–30
25
ns
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