參數(shù)資料
型號： M37542M2-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQCC36
封裝： 6 X 6 MM, 0.50 MM PITCH, PLASTIC, WQFN-36
文件頁數(shù)： 43/122頁
文件大?。?/td> 1311K
代理商： M37542M2-XXXHP
7542 Group
Rev.3.03
Jul 11, 2008
Page 27 of 117
REJ03B0006-0303
b7
b0 Interrupt control register 1
Serial I/O1 receive interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
(ICON1 : address 003E16, initial value : 0016)
b7
b0 Interrupt control register 2
Capture 0 interrupt enable bit
0 : Interrupts disabled
1: Interrupts enabled
(ICON2 : address 003F16, initial value : 0016)
Interrupt request register 2
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ2 : address 003D16, initial value : 0016)
b7
b0
Capture 0 interrupt request bit
Interrupt request register 1
Serial I/O1 receive interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16, initial value : 0016)
b7
b0
Not used (returns “0” when read)
(Do not write “1” to this bit.)
A/D conversion/Timer 1 interrupt enable bit
Timer B interrupt enable bit
Timer A interrupt enable bit
Timer X interrupt enable bit
Compare interrupt enable bit
Capture 1 interrupt enable bit
CNTR0 interrupt enable bit
Key-on wake up/UART1 bus collision
detection interrupt enable bit
INT1 interrupt enable bit
INT0 interrupt enable bit
Serial I/O2 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
A/D conversion/Timer 1 interrupt request bit
Timer B interrupt request bit
Timer A interrupt request bit
Timer X interrupt request bit
Compare interrupt request bit
Capture 1 interrupt request bit
CNTR0 interrupt request bit
Key-on wake up/UART1 bus collision detection
interrupt request bit
INT1 interrupt request bit
INT0 interrupt request bit
Serial I/O2 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Interrupt source set register
(INTSET: address 000A16, initial value: 0016)
Key-on wakeup interrupt valid bit
b7
b0
Interrupt source discrimination register
(INTDIS: address 000B16, initial value: 0016)
Key-on wakeup interrupt discrimination bit
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16, initial value: 0016)
b7
b0
Not used (returns “0” when read)
Timer 1 interrupt valid bit
A/D conversion interrupt valid bit
UART1 bus collision detection interrupt valid bit
1: Interrupt valid
0: Interrupt invalid
1 : Interrupt request issued
0 : No interrupt request issued
Not used (returns “0” when read)
Timer 1 interrupt discrimination bit
A/D conversion interrupt discrimination bit
UART1 bus collision detection
interrupt discrimination bit
INT0 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT1 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT1 input port selection bit (Note 1)
0 : P36
1 : P33
Not used (returns “0” when read)
P00 key-on wakeup selection bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
P04 key-on wakeup selection bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
P06 key-on wakeup selection bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
Fig. 24 Structure of Interrupt-related registers
Note 1: P36 does not exist for the 32-pin version and
the PWQN0036KA-A package.
Select P33 for the INT1 function.
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