參數(shù)資料
型號(hào)： M37540M4-XXXSP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 15/64頁
文件大?。?/td> 668K
代理商： M37540M4-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7540 Group
MITSUBISHI MICROCOMPUTERS
15
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Interrupts
Interrupts occur by 15 different sources : 5 external sources, 9 inter-
nal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by the
interrupt disable flag. When the interrupt enable bit and the interrupt
request bit are set to “1” and the interrupt disable flag is set to “0”, an
interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the in-
terrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status regis-
ter are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
Notes on use
When the active edge of an external interrupt (INT
0
, INT
1
,CNTR
0
) is
set, the interrupt request bit may be set.
Therefore, please take following sequence:
1. Disable the external interrupt which is selected.
2. Change the active edge in interrupt edge selection register. (in
case of CNTR
0
: Timer X mode register, in case of CNTR
1
: Timer
A mode register)
3. Clear the set interrupt request bit to “0”.
4. Enable the external interrupt which is selected.
Table 4 Interrupt vector address and priority
Vector addresses (Note 1)
High-order
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Low-order
Interrupt request generating conditions
At reset input
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge of
INT
0
input
At detection of either rising or falling edge of
INT
1
input
At falling of conjunction of input logical level for
port P0 (at input)
At detection of either rising or falling edge of
CNTR
0
input
At detection of either rising or falling edge of
CNTR
1
input
At timer X underflow
At timer Y underflow
At timer Z underflow
At timer A underflow
At completion of transmit/receive shift
At completion of A-D conversion
At timer 1 underflow
Not available
At BRK instruction execution
Remarks
Non-maskable
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Non-maskable software interrupt
Interrupt source
Reset (Note 2)
Serial I/O1 receive
Serial I/O1 transmit
INT
0
INT
1
(Note 3)
Key-on wake-up
CNTR
0
CNTR
1
Timer X
Timer Y
Timer Z
Timer A
Serial I/O2
A-D conversion
Timer 1
Reserved area
BRK instruction
Note 1:
Vector addressed contain internal jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
3:
It is an interrupt which can use only for 36 pin version.
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
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