參數(shù)資料
型號(hào)： M37540M4-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 50/64頁
文件大?。?/td> 668K
代理商： M37540M4-XXXFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7540 Group
MITSUBISHI MICROCOMPUTERS
50
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Switching Characteristics (General purpose)
Table 13 Switching characteristics (1) (V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
t
C
(S
CLK1
)/2–30
t
C
(S
CLK1
)/2–30
–30
t
C
(S
CLK2
)/2–30
t
C
(S
CLK2
)/2–30
0
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
d
(S
CLK1
–TxD
1
)
t
v
(S
CLK1
–TxD
1
)
t
r
(S
CLK1
)
t
f
(S
CLK1
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
d
(S
CLK2
–S
DATA2
)
t
v
(S
CLK2
–S
DATA2
)
t
r
(S
CLK2
)
t
f
(S
CLK2
)
t
r
(CMOS)
t
f
(CMOS)
Note 1:
Pin X
OUT
is excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Table 14 Switching characteristics (2) (V
CC
= 2.2 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min.
TBD
TBD
Typ.
Max.
Symbol
Parameter
Limits
Unit
TBD
TBD
TBD
350
50
50
50
50
Note 1:
Pin X
OUT
is excluded.
Switching characteristics measurement circuit diagram (Gen-
eral purpose)
/ / /
Measured
output pin
CMOS output
100 pF
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
d
(S
CLK1
–T
x
D
1
)
t
v
(S
CLK1
–T
x
D
1
)
t
r
(S
CLK1
)
t
f
(S
CLK1
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
d
(S
CLK2
–S
DATA2
)
t
v
(S
CLK2
–S
DATA2
)
t
r
(S
CLK2
)
t
f
(S
CLK2
)
t
r
(CMOS)
t
f
(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
TBD
t
C
(S
CLK2
)/2–50
t
C
(S
CLK2
)/2–50
0
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
140
30
30
140
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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