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3
3-14
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
32182 Group User’s Manual (Rev.1.0)
SFR Area Register Map (3/21)
Address
+0 address
+1 address
See
b0
b7 b8
b15
Pages
H'0080 0136
SIO2 Receive Control Register
SIO2 Baud Rate Register
12-19
(S2RCNT)
(S2BAUR)
12-22
(Use inhibited area)
H'0080 0140
SIO3 Transmit Control Register
SIO3 Transmit/Receive Mode Register
12-13
(S3TCNT)
(S3MOD)
12-14
H'0080 0142
SIO3 Transmit Buffer Register
12-17
(S3TXB)
H'0080 0144
SIO3 Receive Buffer Register
12-18
(S3RXB)
H'0080 0146
SIO3 Receive Control Register
SIO3 Baud Rate Register
12-19
(S3RCNT)
(S3BAUR)
12-22
(Use inhibited area)
H'0080 0180
CS0 Area Wait Control Register
CS1 Area Wait Control Register
16-4
(CS0WTCR)
(CS1WTCR)
H'0080 0182
CS2 Area Wait Control Register
CS3 Area Wait Control Register
16-4
(CS2WTCR)
(CS3WTCR)
(Use inhibited area)
H'0080 01E0
Flash Mode Register
Flash Status Register 1
6-5
(FMOD)
(FSTAT1)
6-6
H'0080 01E2
Flash Control Register 1
Flash Control Register 2
6-8
(FCNT1)
(FCNT2)
6-9
H'0080 01E4
Flash Control Register 3
Flash Control Register 4
6-10
(FCNT3)
(FCNT4)
H'0080 01E6
(Use inhibited area)
H'0080 01E8
Virtual Flash S Bank Register 0
6-12
(FESBANK0)
H'0080 01EA
Virtual Flash S Bank Register 1
6-12
(FESBANK1)
H'0080 01EC
Virtual Flash S Bank Register 2
6-12
(FESBANK2)
H'0080 01EE
Virtual Flash S Bank Register 3
6-12
(FESBANK3)
H'0080 01F0
Virtual Flash S Bank Register 4
6-12
(FESBANK4)
H'0080 01F2
Virtual Flash S Bank Register 5
6-12
(FESBANK5)
H'0080 01F4
Virtual Flash S Bank Register 6
6-12
(FESBANK6)
H'0080 01F6
Virtual Flash S Bank Register 7
6-12
(FESBANK7)
(Use inhibited area)
H'0080 0200
(Use inhibited area)
Clock Bus & Input Event Bus Control Register
10-14
(CKIEBCR)
H'0080 0202
Prescaler Register 0
Prescaler Register 1
10-10
(PRS0)
(PRS1)
H'0080 0204
Prescaler Register 2
Output Event Bus Control Register
10-10
(PRS2)
(OEBCR)
10-15
(Use inhibited area)
H'0080 0210
TCLK Input Processing Control Register
10-18
(TCLKCR)
H'0080 0212
TIN0–4 Input Processing Control Register
10-19
(TIN04CR)
(Use inhibited area)
H'0080 0218
TIN12–19 Input Processing Control Register
10-20
(TIN1219CR)
H'0080 021A
TIN20–23, TIN30–33 Input Processing Control Register
10-20
(TIN2023_3033CR)
(Use inhibited area)
H'0080 0220
F/F6–15 Source Select Register
10-22
(FF615S)
H'0080 0222
(Use inhibited area)
F/F16–19 Source Select Register
10-23
(FF1619S)
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