參數(shù)資料
型號(hào)： M37516M6H-XXXKP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, QFN-44
文件頁(yè)數(shù)： 32/65頁(yè)
文件大?。?/td> 1024K
代理商： M37516M6H-XXXKP
35
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7516 Group (Spec. H)
Fig. 36 START condition detecting timing diagram
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 36, 37, and Table 11. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL re-
lease time, setup time, and hold time (see Table 11).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 11, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “IICIRQ” occurs to the CPU.
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I2C status
register (address 002D16) at the same time after writing the slave
address to the I2C data shift register (address 002B16) with the
condition in which the ES0 bit of the I2C control register (address
002E16) and the BB flag are “0”, a START condition occurs. After
that, the bit counter becomes “0002” and an SCL for 1 byte is out-
put. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 34, the START condition generating timing diagram, and
Table 9, the START condition generating timing table.
STOP Condition Generating Method
When the ES0 bit of the I2C control register (address 002E16) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I2C status register (address 002D16) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 35, the STOP condition generating timing
diagram, and Table 10, the STOP condition generating timing
table.
Fig. 34 START condition generating timing diagram
Fig. 35 STOP condition generating timing diagram
Table 10 STOP condition generating timing table
Item
Setup time
Hold time
Standard clock mode
5.0
s (20 cycles)
4.5
s (18 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the
number of
φ cycles.
High-speed clock mode
3.0
s (12 cycles)
2.5
s (10 cycles)
Table 9 START condition generating timing table
Item
Setup time
Hold time
Standard clock mode
5.0
s (20 cycles)
5.0
s (20 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the
number of
φ cycles.
High-speed clock mode
2.5
s (10 cycles)
2.5
s (10 cycles)
Table 11 START condition/STOP condition detecting conditions
Note: Unit : Cycle number of system clock
φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at
φ = 4 MHz.
Fig. 37 STOP condition detecting timing diagram
SCL release time
Standard clock mode
High-speed clock mode
4 cycles (1.0
s)
2 cycles (1.0
s)
2 cycles (0.5
s)
3.5 cycles (0.875
s)
SSC value + 1
2
SSC value + 1
2
SSC value –1
2
Setup time
Hold time
BB flag set/
reset time
SSC value + 1 cycle (6.25
s)
cycle < 4.0
s (3.125 s)
cycle < 4.0
s (3.125 s)
+ 2 cycles (3.375
s)
I2C status register
write signal
Hold time
Setup
time
SCL
SDA
I2C status register
write signal
Hold time
Setup
time
SCL
SDA
Hold time
Setup
time
SCL
SDA
BB flag
SCL release time
BB flag
reset
time
Hold time
Setup
time
SCL
SDA
BB flag
SCL release time
BB flag
reset
time
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