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7480 Group and 7481 Group User's Manual
2-15
APPLICATIONS
Figure 2.2.16 Control Procedure Example of Motorcycle Engine
2.2 Timer X and Timer Y
Initialize
TYM (Address 00F716)
Programmable waveform
generation mode
Output level latch
RESET(Note 1)
0
1
Set timer XY control register
TXYCON (Address 00F816)
Timer X count start
0
SEI
Writing to latch and timer simultaneously
Timer Y
← Initial value (Note 3)
Timer Y interrupt request bit
← 0
Timer Y interrupt enable bit
← 1
CLI
INT1 Interrupt service routine
Change timer Y (Note 3)
RTI
Processing
b0
b7
b0
b7
Timer Y activated by input signal
to INT1 pin
0
Timer Y count source selected
0
Timer Y count start (Note 4)
0
INT1 interrupt request bit
← 0
INT1 interrupt enable bit
← 1
TYM (Address 00F716)
0
1
Writing to latch only
b0
b7
0
11
Change timer Y (Note 3)
Timer Y interrupt service routine
RTI
Stop timer Y counting
TXYCON (Address 00F816)
b0
b7
Timer Y count stop
0
1
After INT1 edge detected,
first timer Y interrupt occurs?
Y
N
Change timer Y output level latch
0
1
b0
b7
0
11
0
Output level latch
After INT1 edge detected,
second timer Y interrupt occurs?
Y
Change timer Y output level latch
0
1
b0
b7
0
11
1
After INT1 edge detected,
third timer Y interrupt occurs?
Y
Timer Y
← Initial value (Note 3)
Control timer Y writing
0
1
b0
b7
0
11
1
Control timer Y writing
0
1
b0
b7
0
11 0
Start Timer Y counting
b0
b7
Timer Y count start (Note 4)
0
N
Notes 1: State after system is released from reset
Timer X and Y stop control bits = 0 (count stopped)
Timer Y and INT1 interrupt enable bits = 0 (disabled)
2: The output level of CNTR1 pin is initialized to LOW.
3: Write to timer Y in order of low-order to high-order byte.
4: In this time, timer Y remains still stopped.
Port P40 (alternative function of CNTR0) is set to input.
Port P41 (alternative function of CNTR1) is set to output.
INT1 edge selection bit
← (rising edge detected)
CNTR0 edge selection bit
← (rise-to-rise period detected)
TXM(Address 00F616)
×× × 01 0
b7
b0
Set timer X mode register
Pulse period measurement mode
Timer X count source selected
Set timer Y mode register (Note 2)
TYM (Address 00F716)
Output level latch
TYM (Address 00F716)
Control timer Y writing
Writing to latch only
TYM (Address 00F716)
Writing to latch and timer
simultaneously
TXYCON (Address 00F816)