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參數(shù)資料
| 型號： | LPC47M192 |
| 廠商： | SMSC Corporation |
| 英文描述： | LPC SUPER I/O WITH HARDWARE MONITORING BLOCK |
| 中文描述： | LPC超級的I / O座硬件監(jiān)測 |
| 文件頁數(shù)： | 7/228頁 |
| 文件大?。?/td> | 1269K |
| 代理商： | LPC47M192 |
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SMSC DS – LPC47M192
Page 7
Rev. 03/30/05
DATASHEET
TABLES
Table 1 – Super I/O Block Addresses.........................................................................................................................27
Table 2 – Status, Data and Control Registers.............................................................................................................31
Table 3 – Internal 2 Drive Decode – Normal...............................................................................................................34
Table 4 – Internal 2 Drive Decode – Drives 0 and 1 Swapped....................................................................................35
Table 5 – Tape Select Bits..........................................................................................................................................35
Table 6 – Drive Type ID ..............................................................................................................................................35
Table 7 – Precompensation Delays ...........................................................................................................................36
Table 8 – Data Rates ..................................................................................................................................................37
Table 9 – DRVDEN Mapping ......................................................................................................................................37
Table 10 – Default Precompensation Delays..............................................................................................................37
Table 11 – FIFO Service Delay..................................................................................................................................39
Table 12 – Status Register 0.......................................................................................................................................41
Table 13 – Status Register 1.......................................................................................................................................41
Table 14 – Status Register 2.......................................................................................................................................42
Table 15 – Status Register 3.......................................................................................................................................42
Table 16 – Description of Command Symbols...........................................................................................................45
Table 17 – Instruction Set ...........................................................................................................................................48
Table 18 – Sector Sizes.............................................................................................................................................54
Table 19 – Effects of MT and N Bits...........................................................................................................................55
Table 20 – Skip Bit vs Read Data Command.............................................................................................................55
Table 21 – Skip Bit vs. Read Deleted Data Command...............................................................................................55
Table 22 – Result Phase Table..................................................................................................................................56
Table 23 – Verify Command Result Phase Table ......................................................................................................57
Table 24 – Typical Values for Formatting...................................................................................................................58
Table 25 – Interrupt Identification...............................................................................................................................60
Table 26 – Drive Control Delays (ms) ........................................................................................................................61
Table 27 – Effects of WGATE and GAP Bits..............................................................................................................63
Table 28 – Addressing the Serial Port........................................................................................................................65
Table 29 – Interrupt Control Table .............................................................................................................................67
Table 30 - Baud Rates ................................................................................................................................................73
Table 31 - Reset Function Table..................................................................................................................................73
Table 32 - Register Summary for an Individual UART Channel..................................................................................74
Table 33 – MPU-401 HOST INTERFACE REGISTERS............................................................................................79
Table 34 - MIDI Data Port ...........................................................................................................................................79
Table 35 - MPU-401 STATUS PORT..........................................................................................................................79
Table 36 – MIDI RECEIVE BUFFER EMPTY STATUS BIT.......................................................................................80
Table 37 - MIDI TRANSMIT BUSY STATUS BIT.........................................................................................................80
Table 38 - MPU-401 COMMAND PORT......................................................................................................................80
Table 39 - Parallel Port Connector...............................................................................................................................83
Table 40 - EPP Pin Descriptions.................................................................................................................................88
Table 41 – ECP Pin Descriptions...............................................................................................................................90
Table 42 - ECP Register Definitions.............................................................................................................................90
Table 43 - Mode Descriptions ......................................................................................................................................91
Table 44a - Extended Control Register........................................................................................................................94
Table 45 - Channel/Data Commands supported in ECP mode....................................................................................96
Table 46 - PC/AT and PS/2 Available Registers..........................................................................................................99
Table 47 - State of System Pins in Auto Powerdown.................................................................................................100
Table 48 - State of Floppy Disk Drive Interface Pins in Powerdown ..........................................................................100
Table 49 - I/O Address Map.......................................................................................................................................106
Table 50 – Host Interface Flags...............................................................................................................................106
Table 51 - Status Register .........................................................................................................................................108
Table 52 - Resets.......................................................................................................................................................109
Table 53 - General Purpose I/O Port Assignments....................................................................................................114
Table 54 - GPIO Configuration Summary ..................................................................................................................115
Table 55 – GPIO Read/Write Behavior ....................................................................................................................116
Table 56 - Different Modes for Fan ............................................................................................................................122
Table 57 - SMBus Write Byte Protocol.......................................................................................................................130
Table 58 - SMBus Read Byte Protocol.......................................................................................................................131
Table 59 - SMBus Send Byte Protocol.......................................................................................................................131
Table 60 - SMBus Receive Byte Protocol ..................................................................................................................131
Table 61 - Modified SMBus Receive Byte Protocol Response to ARA ......................................................................132
Table 62 - Runtime Register Block Summary ............................................................................................................139
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