參數(shù)資料
型號(hào): M37478M4
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁數(shù): 17/47頁
文件大?。?/td> 669K
代理商: M37478M4
17
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit or receive buffer.
Fig. 8 Clock synchronous serial I/O block diagram
Fig. 9 Operation of clock synchronous serial I/O function
Transfer shift clock
(1/8 to 1/8192 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Receive enable signal S
RDY
Write signal to
receive/transmit buffer
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
7
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE) detection
Notes 1 : The transmit interrupt request (TI) can be selected to occur either when the transmit buffer has emptied (TBE = 1) or after the
transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control
register.
2 : If data is written to the transmit buffer when TSC = 0, the transmit clock is generated continuously and serial data is output
continuously from the TxD pin.
3 : The receive interrupt request (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Data bus
Data bus
Receive buffer register
Clock control circuit
Serial I/O control register
Fall detect
Serial I/O status register
F/F
1/4
1/4
1/4
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Serial I/O synchronous
clock selection
bit (SCS)
Frequency dividing
ratio 1/(n+1)
Baud rate generator
P1
6
P1
4
Shift clock
P1
5
P1
7
Clock control circuit
Receive shift register
Transmit shift register
Transmit buffer register
T
X
D
S
RDY
S
CLK
R
X
D
f(X
IN
)
SRDY
Address 00E0
16
Address 00E2
16
Address 00E0
16
Address 00E1
16
Address 00E4
16
CSS
TE
RE
SIOE
TIC
Shift clock
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