參數(shù)資料
型號(hào)： M37477M8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 11/47頁(yè)
文件大?。?/td> 669K
代理商： M37477M8
11
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When the device is put into power-down state by the STP instruc-
tion or the WIT instruction, if bit 5 in the edge polarity selection
register is “1”, the INT
1
interrupt becomes a key on wake up inter-
rupt. When a key on wake up interrupt is valid, an interrupt request
is generated by applying the “L” level to any pin in port P0. In this
case , the port used for interrupt must have been set for the input
mode.
If bit 5 in the edge polarity selection register is “0” when the device
is in power-down state, the INT
1
interrupt is selected. Also, if bit 5
in the edge polarity selection register is set to “1” when the device
is not in a power-down state, neither key on wake up interrupt re-
quest nor INT
1
interrupt request is generated.
The CNTR
0
/CNTR
1
interrupts function in the same as INT
0
and
INT
1
. The interrupt input pin can be specified for either CNTR
0
or
CNTR
1
pin by setting bit 4 in the edge polarity selection register.
Figure 4 shows the structure of the edge polarity selection regis-
ter, interrupt request registers 1 and 2, and interrupt control
registers 1 and 2.
Interrupts other than the BRK instruction interrupt and reset are
accepted when the interrupt enable bit is “1”, interrupt request bit
is “1”, and the interrupt disable flag is “0”. The interrupt request bit
can be reset with a program, but not set. The interrupt enable bit
can be set and reset with a program.
Reset is treated as a non-maskable interrupt with the highest pri-
ority. Figure 5 shows interrupts control.
Interrupt source
RESET
INT
0
interrupt
INT
1
interrupt or key on wake up interrupt
CNTR
0
interrupt or CNTR
1
interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 4 interrupt
Serial I/O receive interrupt
Serial I/O transmit interrupt
A-D conversion completion interrupt
BRK instruction interrupt
Priority
1
2
3
4
5
6
7
8
9
10
11
12
Vector addresses
FFFF
16
, FFFE
16
FFFD
16
, FFFC
16
FFFB
16
, FFFA
16
FFF9
16
, FFF8
16
FFF7
16
, FFF6
16
FFF5
16
, FFF4
16
FFF3
16
, FFF2
16
FFF1
16
, FFF0
16
FFEF
16
, FFEE
16
FFED
16
, FFEC
16
FFEB
16
, FFEA
16
FFE9
16
, FFE8
16
Remarks
Non-maskable
External interrupt (polarity programmable)
External interrupt (INT
1
is polarity programmable)
External interrupt (polarity programmable)
Non-maskable software interrupt
Table 1. Interrupt vector address and priority.
INTERRUPTS
Interrupts can be caused by 13 different sources consisting of five
external, seven internal, and one software sources.
Interrupts are vectored interrupts with priorities shown in Table 1.
Reset is also included in the table because its operation is similar
to an interrupt.
When an interrupt is accepted, the registers are pushed, interrupt
disable flag I is set, and the program jumps to the address speci-
fied in the vector table. The interrupt request bit is cleared
automatically. The reset and BRK instruction interrupt can never
be disabled. Other interrupts are disabled when the interrupt dis-
able flag is set.
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits
are in interrupt request registers 1 and 2 and the interrupt enable
bits are in interrupt control registers 1 and 2. External interrupts
INT
0
and INT
1
can be asserted on either the falling or rising edge
as set in the edge polarity selection register. When “0” is set to this
register, the interrupt is activated on the falling edge; when “1” is
set to the register, the interrupt is activated on the rising edge.
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