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24
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 18 Timing diagram at reset
Fig. 16 Example of reset circuit
Fig. 17 Internal state of microcomputer at reset
(1) Port P0 direction register
(C1
16
) …
(2) Port P1 direction register
(C3
16
) …
(3) Port P4 direction register
(C9
16
) …
(4) P0 pull-up control register
(D0
16
) …
(5)
P1–P5 pull-up control register (Note 1)
(D1
16
) …
(6) Edge selection register (EG)
(D4
16
) …
(7) A-D control register
(D9
16
) …
(8) Serial I/O status register
(E1
16
) …
(9) Serial I/O control register
(E2
16
) …
(10)UART control register
(E3
16
) …
(11)Timer 12 mode register (T12M)
(F8
16
) …
(12)Timer 34 mode register (T34M)
(F9
16
) …
(13)Timer mode register 2 (TM2)
(FA
16
) …
(14)CPU mode register (CM)
(FB
16
) …
(15)Interrupt request register 1
(FC
16
) …
(16)Interrupt request register 2
(FD
16
) …
(17)Interrupt control register 1
(FE
16
) …
(18)Interrupt control register 2
(FF
16
) …
(19)Program counter
(PC
H
) …
(PC
L
) …
(20)Processor status register
(PS) …
00
16
00
16
0 0 0 0
0
0
0 0
0 0 0 0 0 0
0
1 0 0 0
0 0 0 0 0 0 0
0 0 0 0
0 0
0 0
0 0 0 0
0 0 0
0 0
0 0 0 0
0 0 0
0 0
0 0 0 0
0 0 0
1
00
16
00
16
00
16
00
16
Contents of address FFFF
16
Contents of address FFFE
16
Notes 1 : This address is allocated P1–P4 pull-up control register for the
7477 group. Bit 6 is not used.
2 : Since the contents of both registers other than those listed
above (including timers and the transmit/receive buffer register)
are undefined at reset, it is necessary to set initial values.
Address
RESET CIRCUIT
The 7477/7478 group is reset according to the sequence shown in
Figure 18. It starts the program from the address formed by using
the content of address FFFF
16
as the high order address and the
content of the address FFFE
16
as the low order address, when the
RESET pin is held at “L” level for no less than 2
μ
s while the power
voltage is in the recommended operating condition and then re-
turned to “H” level.
The internal initializations following reset are shown in Figure 17.
Example of reset circuit is Figure 16. Immediately after reset, timer
3 and timer 4 are connected, and counts the f(X
IN
) divided by 16.
At this time, FF
16
is set to timer 3, and 07
16
is set to timer 4. The
reset is cleared when timer 4 overflows.
RESET
V
CC
7477/7478 group
00, S
00, S-1
00, S-2
FFFE
16
FFFF
16
AD
H,L
PC
H
PC
L
PS
AD
L
AD
H
X
IN
φ
RESET
Internal
Address
Data
SYNC
32768 counts of f(X
IN
)
Reset address from
the vector table
Notes 1 : Frequency relation of X
IN
and
φ
is f(X
IN
)=2·
φ
.
2 : The mark “” means that the address is changeable depending
upon the previous state.
RESET