參數(shù)資料
型號: M37471M8-XXXFP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 17/46頁
文件大?。?/td> 646K
代理商: M37471M8-XXXFP
17
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
SERIAL I/O
The block diagram of serial I/O is shown in Figure 8. In the serial
I/O mode, the receive ready signal (S
RDY
), synchronous input/out-
put clock (CLK), and the serial I/O (S
OUT
, S
IN
) pins are used as
P1
7
, P1
6
, P1
5
, and P1
4
, respectively.
The serial I/O mode register (address 00DC
16
) is an 8-bit register.
Bit 2 of this register is used to select a synchronous clock source.
When this bit is “0”, an external clock from P1
6
is selected. When
this bit is “1”, an internal clock is selected.
The internal clock can be selected from among the divide by 8, di-
vide by 16, divide by 32, divide by 512 frequency of the oscillator
frequency f(X
IN
) or f(X
CIN
). Do not select f(X
CIN
) as the count
source in the 7470 group. The divide ratio is selected according to
bit 0 and bit 1 in the serial I/O mode register, and selection be-
tween f(X
IN
) and f(X
CIN
) is mode according to bit 7 in the CPU
mode register.
Bits 3 and 4 decide whether parts of P1 will be used as a serial
I/O or not. When bit 3 is “1”, P1
6
becomes an I/O pin of the syn-
chronous clock. When an internal synchronous clock is selected,
the clock is output from P1
6
. If the external synchronous clock is
selected, the clock is input to P1
6
.
And P1
5
will be a serial output. To use P1
4
as a serial input, set
the direction register bit which corresponds to P1
4
, to “0”. For
more information on the direction register, refer to the I/O pin sec-
tion.
Fig. 8 Block diagram of serial I/O
1/2
1/2
1/4
X
CIN
(Note 1)
X
IN
CM
7
Counter
1/2
1/4
1/64
SM
1
SM
0
SM
5
SM
2
Sync. circuit
Serial I/O counter (3)
Byte counter (4)
Serial I/O register (8)
Data bus
CLK input
CLK output
S
IN
S
OUT
S
R
SC
SM
6
Serial I/O
interrupt request
Note 1 :
The 7470 group does not have X
CIN
input.
SA
RDY
S
RDY
Q
( Select gate : At reset, shaded side is connected.)
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