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參數(shù)資料
| 型號： | M37471M2-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 14/46頁 |
| 文件大小： | 646K |
| 代理商： | M37471M2-XXXFP |
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14
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(2) Event count mode
Timer operates in the same way as in the timer mode except that
it counts input from the CNTR
0
or CNTR
1
pin.
(3) Pulse output mode
In this mode, duty 50% pulses are output from the T
0
or T
1
pin.
When the timer overflows, the polarity of the T
0
or T
1
pin output
level is inverted.
(4) Pulse width measuring mode
The 7470/7471 group can measure the “H” or “L” width of the
CNTR
0
or CNTR
1
input waveform by using the pulse width mea-
suring mode of timer 4. The pulse width measuring mode is
selected by writing “1” to bit 6 in the timer 34 mode register. In the
pulse width measuring mode, the timer counts the count source
while the CNTR
0
or CNTR
1
input is “H” or “L”. Whether the CNTR
0
input or CNTR
1
input to be measured can be specified by the sta-
tus of bit 4 in the edge polarity selection register; whether the “H”
width or “L” width to be measured can be specified by the status of
bit 2 (CNTR
0
) and bit 3 (CNTR
1
) in the edge polarity selection reg-
ister.
(5) PWM mode
The PWM mode can be entered for timer 3 and timer 4 by setting
bit 7 in the timer mode register 2 to “1”. In the PWM mode, the P1
3
pin is set for timer output T
1
to output PWM waveforms by setting
bit 7 in the timer 34 mode register to “1”. The direction register of
P1
3
must be set for the output mode before this can be done.
In the PWM mode, timer 3 is counting and timer 4 is idle while the
PWM waveform is “L”. When timer 3 overflows, the PWM waveform
goes “H”. At this time, timer 3 stops counting simultaneously and
timer 4 starts counting. When timer 4 overflows, the PWM wave-
form goes “L”, and timer 4 stops and timer 3 starts counting again.
Consequently, the “L” duration of the PWM waveform is deter-
mined by the value of timer 3; the “H” duration of the PWM
waveform is determined by the value of timer 4.
When a value is written to the timer in operation during the PWM
mode, the value is only written to the timer latch, and not written to
the timer. In this case, if the timer overflows, a value one less the
value in the timer latch is written to the timer. When any value is
written to an idle timer, the value is written to both the timer latch
and the timer.
In this mode, do not select timer 3 overflow as the count source for
timer 4.
INPUT LATCH FUNCTION
The 7470/7471 group can latch the P3
0
/INT
0
, P3
1
/INT
1
, P3
2
/
CNTR
0
, and P3
3
/CNTR
1
pin level into the input latch register (ad-
dress 00D6
16
) when timer 4 overflows. The polarity of each pin
latched to the input latch register can be selected by using the
edge polarity selection register. When bit 0 in the edge polarity se-
lection register is “0”, the inverted value of the P3
0
/INT
0
pin level is
latched; when the bit is “1”, the P3
0
/INT
0
pin level is latched as it
is. When bit 1 in the edge polarity selection register is “0”, the in-
verted value of the P3
1
/INT
1
pin level is latched; when the bit is
“1”, the P3
1
/INT
1
pin level is latched as it is. When bit 2 in the edge
polarity selection register is “0”, the inverted value of the P3
2
/
CNTR
0
pin level is latched; when the bit is “1”, the P3
2
/CNTR
0
pin
level is latched as it is. When bit 3 in the edge polarity selection
register is “0”, the inverted value of the P3
3
/CNTR
1
pin level is
latched; when the bit is “1”, the P3
3
/CNTR
1
pin level is latched as
it is.
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