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參數資料
| 型號： | M37470M2-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | SHRINK, PLASTIC, DIP-32 |
| 文件頁數： | 9/46頁 |
| 文件大小： | 646K |
| 代理商： | M37470M2-XXXSP |
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17
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
SERIAL I/O
The block diagram of serial I/O is shown in Figure 8. In the serial
I/O mode, the receive ready signal (SRDY), synchronous input/out-
put clock (CLK), and the serial I/O (SOUT, SIN) pins are used as
P17, P16, P15, and P14, respectively.
The serial I/O mode register (address 00DC16) is an 8-bit register.
Bit 2 of this register is used to select a synchronous clock source.
When this bit is “0”, an external clock from P16 is selected. When
this bit is “1”, an internal clock is selected.
The internal clock can be selected from among the divide by 8, di-
vide by 16, divide by 32, divide by 512 frequency of the oscillator
frequency f(XIN) or f(XCIN). Do not select f(XCIN) as the count
source in the 7470 group. The divide ratio is selected according to
bit 0 and bit 1 in the serial I/O mode register, and selection be-
tween f(XIN) and f(XCIN) is mode according to bit 7 in the CPU
mode register.
Bits 3 and 4 decide whether parts of P1 will be used as a serial
I/O or not. When bit 3 is “1”, P16 becomes an I/O pin of the syn-
chronous clock. When an internal synchronous clock is selected,
the clock is output from P16. If the external synchronous clock is
selected, the clock is input to P16.
And P15 will be a serial output. To use P14 as a serial input, set
the direction register bit which corresponds to P14, to “0”. For
more information on the direction register, refer to the I/O pin sec-
tion.
Fig. 8 Block diagram of serial I/O
1/2
1/4
XCIN
(Note 1)
XIN
CM7
Counter
1/2
1/4
1/64
SM1
SM0
SM5
SM2
Sync. circuit
Serial I/O counter (3)
Byte counter (4)
Serial I/O register (8)
Data bus
CLK input
CLK output
SIN
SOUT
S
R
SC
SM6
Serial I/O
interrupt request
Note 1 : The 7470 group does not have XCIN input.
SARDY
SRDY
Q
(
Select gate : At reset, shaded side is connected.)
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