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參數(shù)資料
| 型號： | M37470M2-XXXSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 18/46頁 |
| 文件大小： | 646K |
| 代理商： | M37470M2-XXXSP |
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18
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Bit 4 determines if P1
7
is used as an output pin for the receive
ready signal (bit 4=“1”, S
RDY
) or used as a normal I/O pin (bit
4=“0”).
When the P1
7
pin is used as the S
RDY
output pin, output signal
can be selected between S
RDY
signal and SA
RDY
signal by using
bit 5 in the serial I/O mode register. The S
RDY
signal is driven “L”
by a signal written into the serial I/O register to inform that the de-
vice is ready to receive. Then, the S
RDY
signal is driven “H” on the
first falling edge of the transfer clock.
The SA
RDY
signal is driven “H” by a signal written into the serial
I/O register, and driven “L” on the last rising edge of the transfer
clock.
The function of serial I/O differs depending on the clock source;
external clock or internal clock.
Internal Clock – The serial I/O counter is set to 7 when data is
stored in the serial I/O register. At each falling edge of the transfer
clock, serial data is output to P1
5
. During the rising edge of this
clock, data can be input from P1
4
and the data in the serial I/O
register will be shifted 1 bit. Data is output starting with the LSB.
After the transfer clock has counted 8 times, the serial I/O register
will be empty and the transfer clock will remain at a high level. At
this time the interrupt request bit will be set.
External Clock – If an external clock is used, the interrupt request
bit will be set after the transfer clock has counted 8 times but the
transfer clock will not stop. Due to this reason, the external clock
must be controlled from the outside.
Timing diagrams are shown in Figure 9.
Fig. 9 Serial I/O timing
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Synchronous clock
Transfer clock
Serial I/O register write
signal
Serial I/O output
S
OUT
Serial I/O input
S
IN
Interrupt request bit set
Receive ready signal
S
RDY
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