參數(shù)資料
型號： M37281MKH-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52
封裝： PLASTIC, SHRINK, DIP-52
文件頁數(shù)： 88/158頁
文件大?。?/td> 1472K
代理商： M37281MKH-XXXSP
35
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
M37281MAH–XXXSP,M37281MFH–XXXSP
M37281MKH–XXXSP,M37281EKSP
8.6.2 I2C Address Register
The I2C address register (address 00F716) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition are detected.
(1) Bit 0: Read/Write Bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I2C
address register.
The RBW bit is cleared to “0” automatically when the STOP condi-
tion is detected.
(2) Bits 1 to 7: Slave Address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
Fig. 8.6.3 I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Read/write bit
(RBW)
1
to
7
Slave address
(SAD0 to SAD6)
<Only in 10-bit addressing (in slave) mode>
The last significant bit of address data is
compared.
0: Wait the first byte of slave address after
START condition
(read state)
1: Wait the first byte of slave address after
RESTART condition
(write state)
<In both modes>
The address data is compared.
I2C Address Register
I2C address register (S0D) [Address 00F716]
B
Name
Functions
0
After reset R W
R —
R W
相關(guān)PDF資料
PDF描述
M37281MAH-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52
M37281MFH-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52
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