參數(shù)資料
型號: M37281MFH-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP52
封裝: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-52
文件頁數(shù): 133/174頁
文件大小: 1420K
代理商: M37281MFH-XXXSP
Rev.1.01
2003.07.16
page 59 of 170
M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
8.10.5 Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large
as the horizontal synchronous signal frequency. It also generates
various timing signals on the basis of the reference clock, horizontal
synchronous signal and vertical synchronizing signal. The circuit
operates by setting bit 0 of data slicer control register 1 (address
00E016) to “1.”
The reference clock can be used as a display clock for OSD function
in addition to the data slicer. The HSYNC signal can be used as a
count source instead of the composite sync signal. However, when
the HSYNC signal is selected, the data slicer cannot be used. A count
source of the reference clock can be selected by bit 2 of data slicer
control register 1 (address 00E016).
For the pins HLF, connect a resistor and a capacitor as shown in
Figure 8.10.1. Make the length of wiring which is connected to these
pins as short as possible so that a leakage current may not be gener-
ated.
Note: It takes a few tens of milliseconds until the reference clock becomes
stable after the data slicer and the timing signal generating circuit are
started. In this period, various timing signals, Hsep signals and Vsep sig-
nals become unstable. For this reason, take stabilization time into con-
sideration when programming.
Fig. 8.10.7 Determination of V-pulse Waveform
Composite
sync signal
A
B
0
1
Bit 5 of DSC2
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