參數(shù)資料
型號： M37281MAH-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP52
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-52
文件頁數(shù)： 147/172頁
文件大?。?/td> 1319K
代理商： M37281MAH-XXXSP
M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Rev.1.01
2003.07.16
page 76 of 170
Fig. 8.11.10 Vertical Position Register 1i (i = 1 to 16)
The vertical start position for each block can be set in 1024 steps
(where each step is 1TH (TH: HSYNC cycle)) as values “0016” to “FF16”
in vertical position register 1i (i = 1 to 16) (addresses 022016 to 022F16)
and values “0016” to “0316” in vertical position register 2i (i = 1 to 16)
(addresses 023016 to 023F16). The vertical position registers are
shown in Figures 8.11.10 and 8.11.11.
Fig. 8.11.11 Vertical Position Register 2i (i = 1 to 16)
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 022016 to 022F16]
B
Name
Functions
After reset RW
Vertical Position Register 1i
0
to
7
Control bits of
vertical display
start positions
(VP1i0 to VP1i7)
(See note 1)
Vertical display start positions
(low-order 8 bits)
TH
(setting value of low-order 2 bits of VP2i 162
+ setting value of low-order 4 bits of VP1i 161
+ setting value of low-order 4 bits of VP1i 160)
RW
Notes 1: Do not “0016” and “0116” to VP1i at VP2i = “00 16.”
2: TH is cycle of HSYNC.
3: VP2i is vertical position register 2i.
Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 023016 to 023F16]
B
Name
Functions
After reset R W
Vertical Position Register 2i
0,
1
Control bits of
vertical display
start positions
(VP2i0, VP2i1)
(See note 1)
Vertical display start positions
(high-order 2 bits)
TH
(setting value of low-order 2 bits of VP2i 162
+ setting value of low-order 4 bits of VP1i 161
+ setting value of low-order 4 bits of VP1i 160)
RW
Nothing ic assigned. These bits are write disable bits.
When these bits are read out, the values are indeterminate.
2
to
7
R —
Notes 1: Do not set “0016” and “0116” to VP1i at VP2i = “00 16.”
2: TH is cycle of HSYNC.
3: VP1i is vertical position register 1i.
Indeterminate
相關(guān)PDF資料
PDF描述
M37281EKSP 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52
M37281MFH-XXXSP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP52
M37281MAH-XXXSP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP52
M37281MKH-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52
M37281MAH-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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