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7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Rev. 1.0
V
CC
,
AV
CC
,
V
SS
CNV
SS
RESET
X
IN
X
OUT
P0
0
/
PWM4–
P0
2
/PWM6,
P0
3
/PWM7,
P0
4
/
PWM0–
P0
7
/PWM3
P10/OUT2,
P11/SCL1,
P12/SCL2,
P13/SDA1,
P14/SDA2,
P15/G0,
P16/INT3/
B0,
P17/S
IN
/R0
P2
0
–P2
3
P2
4
/AD3–
P2
6
/AD1
,
P2
7
/AD5
P3
0
/AD7,
P3
1
/AD8
P3
2
P4
0
/AD4,
P4
1
/INT2,
P4
2
/TIM2,
P4
3
/TIM3,
P4
4
/INT1,
P4
5
/S
OUT
,
P4
6
/S
CLK
P4
7
Input
Input
Input
Output
I/O
Output
I/O
Output
Output
Input
Input
I/O
Input
I/O
Input
Output
Input
Input
Input
Input
Output
I/O
Output
Apply voltage of 5 V ± 10 % (typical) to V
CC
and AV
CC
, and 0 V to V
SS
.
Connected to V
SS
.
To enter the reset state, the reset input pin must be kept at a LOW for 2
μ
s or more (under
normal V
CC
conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an exter-
nal ceramic resonator or a quartz-crystal oscillator is connected between pins X
IN
and X
OUT
.
If an external clock is used, the clock source should be connected to the X
IN
pin and the
X
OUT
pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
of P0
3
is CMOS output, that of P0
0
–P0
2
and P0
4
–P0
7
are N-channel open-drain output. See
notes at end of Table for full details of port P0 functions.
Pins P0
0
–P0
3
and P0
4
–P0
7
are also used as 8-bit PWM output pins PWM4–PWM7 and
PWM0–PWM3 respectively. The output structure of PWM0–PWM6 is N-channel open-drain
output. And the output structure of PWM7 is CMOS output.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure of P1
0
and P1
5
–P1
7
is CMOS output, that of P1
1
–P1
4
is N-channel open-drain
output.
Pin P1
0
, P1
5
–P1
7
are also used as OSD output pins OUT2, G0, B0, R0, respectively. The
output structure is CMOS output.
Pin P1
1
–P1
4
are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I
2
C-BUS interface is used. The output structure is N-channel open-drain output.
Pin P1
6
is also used as extemal interrupt input pin INT3.
Pin P1
7
is also used as serial I/O data input pin S
IN
.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P2
4
–P2
6
, P2
7
are also used as analog input pins AD3–AD1, AD5 respectively.
Ports P3
0
and P3
1
are 2-bit I/O ports and have basically the same functions as port P0. The
output structure is CMOS output.
Pins P3
0
, P3
1
are also used as analog input pins AD7, AD8 respectively.
Ports P3
2
is a 1-bit output port. The output structure is N-channel open-drain output.
Ports P4
0
–P4
6
are a 7-bit input port.
Pin P4
0
is also used as analog input pin AD4.
Pins P4
1
, P4
4
Pins P4
2
and P4
3
are also used as external clock input pins TIM2, TIM3 respectively.
Pin P4
5
is used as serial I/O data output pin S
OUT
. The output structure is N-channel open-
drain output.
Pin P4
6
is used as serial I/O synchronous clock input/output pin S
CLK
. The output structure
is N-channel open-drain output.
Port P4
7
is a 1-bit output port. The output structure is N-channel open-drain output.
Pin
Name
Functions
Input/
Output
Power source
CNV
SS
Reset input
Clock input
Clock output
I/O port P0
8-bit PWM output
I/O port P1
OSD output
Multi-master
I
2
C-BUS interface
External interrupt
input
Serial I/O data
input
I/O port P2
Analog input
I/O port P3
Analog input
Output port P3
Input port P4
Analog input
External interrupt
input
External clock input
Serial I/O data
output
Serial I/O
synchronous clock
input/output
Output port P4
11. PIN DESCRIPTION
Table 11.1 Pin Description