
103
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
CLOCK GENERATING CIRCUIT
The M37274EFSP has 2 built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between X
IN
and
X
OUT
(X
CIN
and X
COUT
). Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No external re-
sistor is needed between X
IN
and X
OUT
since a feed-back resistor
exists on-chip. However, an external feed-back resistor is needed
between X
CIN
and X
COUT
. When using X
CIN
-X
COUT
as sub-clock,
clear bits 5 and 4 of the clock source control register to “0.” To supply
a clock signal externally, input it to the X
IN
(X
CIN
) pin and make the
X
OUT
(X
COUT
) pin open. When not using X
CIN
clock, connect the
X
CIN
to V
SS
and make the X
COUT
pin open.
After reset has completed, the internal clock
φ
is half the frequency of
X
IN
. Immediately after poweron, both the X
IN
and X
CIN
clock start
oscillating. To set the internal clock
φ
to low-speed operation mode,
set bit 7 of the CPU mode register (address 00FB
16
) to “1.”
Oscillation Control
(1) Stop mode
The built-in clock generating circuit is shown in Figure 95. When the
STP instruction is executed, the internal clock
φ
stops at HIGH. At
the same time, timers 3 and 4 are connected by hardware and “FF
16
”
is set in timer 3 and “07
16
” is set in timer 4. Select f(X
IN
)/16 or f(X
CIN
)/
16 as the timer 3 count source (set both bit 0 of the timer mode
register 2 and bit 6 at address 00C7
16
to “0” before the execution of
the STP instruction). Moreover, set the timer 3 and timer 4 interrupt
enable bits to disabled (“0”) before execution of the STP instruction.
The oscillator restarts when external interrupt is accepted. However,
the internal clock
φ
keeps its “H” level until timer 4 overflows, allow-
ing time for oscillation stabilization when a ceramic resonator or a
quartz-crystal oscillator is used.
(2) Wait mode
When the WIT instruction is executed, the internal clock
φ
stops in
the “H” level but the oscillator continues running. This wait state is
released at reset or when an interrupt is accepted (Note). Since the
oscillator does not stop, the next instruction can be executed at once.
Note:
In the wait mode, the following interrupts are invalid.
(1) V
SYNC
interrupt
(2) OSD interrupt
(3) Timers 1 and 2 interrupts using TIM2 pin input as count
source
(4) Timer 3 interrupt using TIM3 pin input as count source
(5) Data slicer interrupt
(6) Multi-master I
2
C-BUS interface interrupt
(7) f(X
IN
)/4096 interrupt
(8) All timer interrupts using f(X
IN
)/2 or f(X
CIN
)/2 as count source
(9) All timer interrupts using f(X
IN
)/4096 or f(X
CIN
)/4096 as
count source
(10) A-D conversion interrupt
Fig. 107. Ceramic Resonator Circuit Example
Fig. 108. External Clock Input Circuit Example
(3) Low-Speed Mode
If the internal clock is generated from the sub-clock (X
CIN
), a low
power consumption operation can be realized by stopping only the
main clock X
IN
. To stop the main clock, set bit 6 (CM
6
) of the CPU
mode register (00FB
16
) to “1.” When the main clock X
IN
is restarted,
the program must allow enough time to for oscillation to stabilize.
Note that in low-power-consumption mode the X
CIN
-X
COUT
drivability
can be reduced, allowing even lower power consumption. To reduce
the X
CIN
-X
COUT
drivability, clear bit 5 (CM
5
) of the CPU mode regis-
ter (00FB
16
) to “0.” At reset, this bit is set to “1” and strong drivability
is selected to help the oscillation to start. When an STP instruction is
executed, set this bit to “1” by software before executing.
X
CIN
X
IN
C
CIN
M37274EFSP
X
COUT
R
f
R
d
C
COUT
X
OUT
C
IN
C
OUT
X
CIN
M37274EFSP
External oscillation
circuit or external
pulse
X
COUT
X
IN
X
OUT
Open
Open
External oscillation
circuit
Vcc
Vss
Vcc
Vss