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  • 參數(shù)資料
    型號: M37273E8SP
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52
    封裝: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-52
    文件頁數(shù): 72/141頁
    文件大?。?/td> 1736K
    代理商: M37273E8SP
    33
    SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
    and ON-SCREEN DISPLAY CONTROLLER
    M37273M8–XXXSP, M37273MF–XXXSP
    M37273E8SP, M37273EFSP
    MITSUBISHI MICROCOMPUTERS
    Rev. 1.0
    8.6.4 I2C Control Register
    The I2C control register (address 00F916) controls the data commu-
    nication format.
    (1) Bits 0 to 2: bit counter (BC0–BC2)
    These bits decide the number of bits for the next 1-byte data to be
    transmitted. An interrupt request signal occurs immediately after the
    number of bits specified with these bits are transmitted.
    When a START condition is received, these bits become “0002” and
    the address data is always transmitted and received in 8 bits.
    (2) Bit 3: I2C interface use enable bit (ESO)
    This bit enables usage of the multimaster I2C BUS interface. When
    this bit is set to “0,” the use disable status is provided, so the SDA
    and the SCL become high-impedance. When the bit is set to “1,” use
    of the interface is enabled.
    When ESO = “0,” the following is performed.
    PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C
    status register at address 00F816 ).
    Writing data to the I2C data shift register (address 00F616) is dis-
    abled.
    (3) Bit 4: data format selection bit (ALS)
    This bit decides whether or not to recognize slave addresses. When
    this bit is set to “0,” the addressing format is selected, so that ad-
    dress data is recognized. When a match is found between a slave
    address and address data as a result of comparison or when a gen-
    eral call (refer to “8.6.5 I2C Status Register,” bit 1) is received, trans-
    mission processing can be performed. When this bit is set to “1,” the
    free data format is selected, so that slave addresses are not recog-
    nized.
    (4) Bit 5: addressing format selection bit (10BIT SAD)
    This bit selects a slave address specification format. When this bit is
    set to “0,” the 7-bit addressing format is selected. In this case, only
    the high-order 7 bits (slave address) of the I2C address register (ad-
    dress 00F716) are compared with address data. When this bit is set
    to “1,” the 10-bit addressing format is selected, all the bits of the I2C
    address register are compared with address data.
    (5) Bits 6 and 7: connection control bits between
    I2C-BUS interface and ports
    (BSEL0, BSEL1)
    These bits controls the connection between SCL and ports or SDA
    and ports (refer to Figure 8.6.5).
    Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1
    Note: Set the corresponding direction register to “1” to use the
    port as multi-master I2C-BUS interface.
    “0”
    “1” BSEL0
    SCL/P11
    SCL2/P12
    “0”
    “1” BSEL1
    “0”
    “1” BSEL0
    SDA1/P13
    SDA2/P14
    “0”
    “1” BSEL1
    Multi-master
    I2C-BUS
    interface
    SCL
    SDA
    相關(guān)PDF資料
    PDF描述
    M37273MF-XXXSP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP52
    M37273EFSP 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52
    M37273M8-XXXSP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP52
    M3727GM8-XXXSP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP42
    M3727GM8-XXXFP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42
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