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| 型號： | M37272MFH |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數(shù)： | 36/131頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | M37272MFH |
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36
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH
–
XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev 1.0
(8) Bit 7: Communication mode specification bit
(master/slave specification bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the
clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
Immediately after completion of 1-byte data transmission when
arbitration lost is detected
When a STOP condition is detected.
When occurence of a START condition is disabled by the START
condition duplication preventing function (Note).
At reset
Fig. 8.6.7 I
2
C Status Register
7 b
6 b5 b4 b
3 b
2 b
1 b
0
I
2
C
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
1
)
[
A
d
d
r
e
s
s
0
0
F
8
1
6
]
I
2
C
S
t
a
t
u
s
R
e
g
i
s
t
e
r
0
3
4
5
6, 7
b
7
0
0
1
1
b
0
1
0
1
6
:
:
:
:
S
S
M
M
l
l
a
a
a
a
v
v
s
s
e
e
t
e
t
e
r
t
r
r
e
r
r
t
c
i
e
s
c
a
v
m
i
e
n
s
e
t
e
m
m
m
i
t
o
d
o
o
m
e
d
d
o
a
n
i
e
e
d
e
r
v
m
e
1
2
0
0
0
1
0
B
N
a
m
e
F
u
n
c
t
i
o
n
s
A
f
t
e
r
r
e
s
e
t
R W
C
s
(
o
p
T
m
e
R
m
i
f
X
u
c
,
n
a
M
i
i
S
c
o
a
n
T
t
i
o
b
n
i
t
m
s
o
d
e
c
i
t
)
0
1
:
B
B
u
u
s
s
f
b
r
e
u
e
s
:
y
B
u
s
b
u
s
y
f
l
a
g
(
B
B
)
0
1
:
I
N
n
t
o
e
r
i
r
u
t
p
t
r
u
r
e
p
q
t
u
r
e
e
s
q
t
i
e
s
s
u
t
e
s
d
s
:
n
e
r
u
s
i
u
e
d
I
2
C
r
e
-
u
B
e
U
s
S
t
i
i
n
t
t
(
e
P
r
f
I
a
N
c
)
e
i
n
t
e
r
r
u
p
t
q
b
0
1
:
N
D
o
e
t
t
e
d
e
t
t
e
e
d
c
t
e
d
:
c
A
(
A
r
b
L
i
)
t
r
(
a
S
t
i
e
o
n
n
l
o
o
s
t
t
)
d
e
t
e
c
t
i
n
g
f
l
a
g
e
e
0
1
:
A
A
d
d
d
d
r
r
e
e
s
s
s
s
m
m
i
a
s
m
t
c
a
h
t
c
h
:
S
f
l
l
a
g
v
e
(
a
A
d
S
d
r
e
(
s
S
s
e
e
c
o
n
m
o
p
t
e
a
)
r
i
s
o
n
a
A
)
0
1
:
N
G
o
e
n
g
e
e
n
r
a
e
l
r
c
a
a
l
l
c
l
a
d
l
e
l
t
d
e
e
c
t
t
e
e
c
d
t
e
d
:
G
(
A
e
n
e
0
r
)
a
(
l
S
c
e
a
e
l
l
n
d
o
e
t
t
e
e
)
c
t
i
n
g
f
l
a
g
D
0
1
:
L
L
a
a
s
s
t
t
b
b
i
i
t
t
=
=
“
“
0
1
”
”
:
L
(
a
S
s
e
t
e
r
e
n
c
o
e
t
e
i
v
)
e
b
i
t
(
L
R
B
)
Note :
These bits and flags can be read out, but cannnot be written.
Indeterminate
R
—
R
—
R
—
R
—
R W
R W
0
R W
(See note)
(See note)
(See note)
(See note)
Fig. 8.6.8 Interrupt Request Signal Generation Timing
SCL
P
I
N
II
C
I
R
Q
Note:
The START condition duplication prevention function disables the START
condition generation, reset of bit counter reset, and SCL output, when
the following condition is satisfied:
a START condition is set by another master device.
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